Merge remote-tracking branch 'up/master' into sse4.1

Author: p32blo

.appveyor.yml

@@ -19,8 +19,7 @@ install:
 build: false
 
 test_script:
-  - cargo test --target %TARGET%
-  - cargo test --target %TARGET% --release
+  - C:\msys64\usr\bin\sh ci\run.sh
 
 branches:
   only:

ci/run.sh

@@ -2,5 +2,12 @@
 
 set -ex
 
+# FIXME(rust-lang/rust#45201) shouldn't need to specify one codegen unit
+export RUSTFLAGS="$RUSTFLAGS -C codegen-units=1"
+
+# Tests are all super fast anyway, and they fault often enough on travis that
+# having only one thread increases debuggability to be worth it.
+export RUST_TEST_THREADS=1
+
 cargo test --target $TARGET
 cargo test --release --target $TARGET

src/arm/v6.rs

@@ -19,3 +19,26 @@ pub unsafe fn _rev_u16(x: u16) -> u16 {
 pub unsafe fn _rev_u32(x: u32) -> u32 {
     x.swap_bytes() as u32
 }
+
+#[cfg(test)]
+mod tests {
+    use stdsimd_test::simd_test;
+
+    use arm::v6;
+
+    #[test]
+    fn _rev_u16() {
+        unsafe {
+            assert_eq!(v6::_rev_u16(0b0000_0000_1111_1111_u16), 0b1111_1111_0000_0000_u16);
+        }
+    }
+
+    #[test]
+    fn _rev_u32() {
+        unsafe {
+            assert_eq!(v6::_rev_u32(
+                0b0000_0000_1111_1111_0000_0000_1111_1111_u32
+            ), 0b1111_1111_0000_0000_1111_1111_0000_0000_u32);
+        }
+    }
+}

src/arm/v7.rs

@@ -42,3 +42,40 @@ extern "C" {
     #[link_name="llvm.bitreverse.i32"]
     fn rbit_u32(i: i32) -> i32;
 }
+
+
+#[cfg(test)]
+mod tests {
+    use stdsimd_test::simd_test;
+
+    use arm::v7;
+
+    #[test]
+    fn _clz_u8() {
+        unsafe {
+            assert_eq!(v7::_clz_u8(0b0000_1010u8), 4u8);
+        }
+    }
+
+    #[test]
+    fn _clz_u16() {
+        unsafe {
+            assert_eq!(v7::_clz_u16(0b0000_1010u16), 12u16);
+        }
+    }
+
+    #[test]
+    fn _clz_u32() {
+        unsafe {
+            assert_eq!(v7::_clz_u32(0b0000_1010u32), 28u32);
+        }
+    }
+
+    #[test]
+    fn _rbit_u32() {
+        unsafe {
+            assert_eq!(v7::_rbit_u32(0b0000_1010u32),
+                       0b0101_0000_0000_0000_0000_0000_0000_0000u32);
+        }
+    }
+}

src/arm/v8.rs

@@ -53,3 +53,53 @@ pub unsafe fn _cls_u32(x: u32) -> u32 {
 pub unsafe fn _cls_u64(x: u64) -> u64 {
     u64::leading_zeros(((((((x as i64) >> 63) as u64) ^ x) << 1) | 1)) as u64
 }
+
+#[cfg(test)]
+mod tests {
+    use stdsimd_test::simd_test;
+
+    use arm::v8;
+
+    #[test]
+    fn _rev_u64() {
+        unsafe {
+            assert_eq!(v8::_rev_u64(
+                0b0000_0000_1111_1111_0000_0000_1111_1111_u64
+            ), 0b1111_1111_0000_0000_1111_1111_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_u64);
+        }
+    }
+
+    #[test]
+    fn _clz_u64() {
+        unsafe {
+            assert_eq!(v8::_clz_u64(0b0000_1010u64), 60u64);
+        }
+    }
+
+    #[test]
+    fn _rbit_u64() {
+        unsafe {
+            assert_eq!(v8::_rbit_u64(
+                0b0000_0000_1111_1101_0000_0000_1111_1111_u64
+            ), 0b1111_1111_0000_0000_1011_1111_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_u64);
+        }
+    }
+
+    #[test]
+    fn _cls_u32() {
+        unsafe {
+            assert_eq!(v8::_cls_u32(
+                0b1111_1111_1111_1111_0000_0000_1111_1111_u32
+            ), 15_u32);
+        }
+    }
+
+    #[test]
+    fn _cls_u64() {
+        unsafe {
+            assert_eq!(v8::_cls_u64(
+                0b1111_1111_1111_1111_0000_0000_1111_1111_0000_0000_0000_0000_0000_0000_0000_0000_u64
+            ), 15_u64);
+        }
+    }
+}

src/lib.rs

@@ -66,7 +66,7 @@
 //! After verifying that a specified feature is available, use `target_feature`
 //! to enable a given feature and use the desired intrinsic.
 //!
-//! ```
+//! ```ignore
 //! # #![feature(cfg_target_feature)]
 //! # #![feature(target_feature)]
 //! # #[macro_use]