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Sub-optimal codegen for float newtypes #32031

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@bsteinb

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@bsteinb

It seems that floating point types wrapped in newtypes are passed to functions in general purpose registers instead of SIMD registers the way plain f32 and f64 are. Consider this code example in playpen.

Without inlining, add_f32() and add_f64() compile to a single instruction (plus return) while add_newtype_{f32|f64}() first have to move their arguments from a general purpose register perform the addition and move the result back to the GPR.

With inlining, the situation is better, but still not optimal. Once again, the functions defined on plain types work directly in SIMD registers and the loop now gets unrolled by a factor of 10. For the newtypes, the accumulator is still kept in a GPR, however the loop is unrolled by a factor of 5. Here, the accumulator is only moved from the GPR to a SIMD register at the start of a loop iteration and moved back at the end (after 5 additions have been performed).

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A-codegenArea: Code generationE-needs-testCall for participation: An issue has been fixed and does not reproduce, but no test has been added.

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