Cherry-pick improvements for AVR codegen

lld/test/ELF/avr-flags.s

@@ -11,7 +11,9 @@
 ; RUN: not ld.lld %t-v5 %t-xmega3 -o /dev/null 2>&1 | FileCheck --check-prefix ERR %s
 ; ERR: error: {{.*}}: cannot link object files with incompatible target ISA
 
-; V5:  Flags [ (0x5)
+; V5:  Flags [ (0x85)
 ; V5:  EF_AVR_ARCH_AVR5 (0x5)
-; XMEGA3: Flags [ (0x67)
+; V5:  EF_AVR_LINKRELAX_PREPARED (0x80)
+; XMEGA3: Flags [ (0xE7)
 ; XMEGA3: EF_AVR_ARCH_XMEGA3 (0x67)
+; XMEGA3: EF_AVR_LINKRELAX_PREPARED (0x80)

lld/test/ELF/linkerscript/avr5.test

@@ -16,7 +16,7 @@
 # RUN: llvm-readelf --headers %t/avr5b.out | FileCheck %s --check-prefix=HEAD
 
 # HEAD: Atmel AVR 8-bit microcontroller
-# HEAD: 0x5, EF_AVR_ARCH_AVR5
+# HEAD: 0x85, EF_AVR_ARCH_AVR5, relaxable
 
 # HEAD:      Name     Type      Address   Off     Size
 # HEAD-NEXT:          NULL      00000000  000000  000000

llvm/lib/Target/AVR/AVRAsmPrinter.cpp

@@ -101,56 +101,51 @@ bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
                                     const char *ExtraCode, raw_ostream &O) {
   // Default asm printer can only deal with some extra codes,
   // so try it first.
-  bool Error = AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
-
-  if (Error && ExtraCode && ExtraCode[0]) {
-    if (ExtraCode[1] != 0)
-      return true; // Unknown modifier.
+  if (!AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O))
+    return false;
 
-    if (ExtraCode[0] >= 'A' && ExtraCode[0] <= 'Z') {
-      const MachineOperand &RegOp = MI->getOperand(OpNum);
+  const MachineOperand &MO = MI->getOperand(OpNum);
 
-      assert(RegOp.isReg() && "Operand must be a register when you're"
-                              "using 'A'..'Z' operand extracodes.");
-      Register Reg = RegOp.getReg();
+  if (ExtraCode && ExtraCode[0]) {
+    // Unknown extra code.
+    if (ExtraCode[1] != 0 || ExtraCode[0] < 'A' || ExtraCode[0] > 'Z')
+      return true;
 
-      unsigned ByteNumber = ExtraCode[0] - 'A';
+    // Operand must be a register when using 'A' ~ 'Z' extra code.
+    if (!MO.isReg())
+      return true;
 
-      unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
-      unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
-      (void)NumOpRegs;
+    Register Reg = MO.getReg();
 
-      const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
-      const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
+    unsigned ByteNumber = ExtraCode[0] - 'A';
+    unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
+    unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
 
-      const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
-      unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
-      assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
+    const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
+    const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
 
-      unsigned RegIdx = ByteNumber / BytesPerReg;
-      if (RegIdx >= NumOpRegs)
-        return true;
-      Reg = MI->getOperand(OpNum + RegIdx).getReg();
+    const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
+    unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
+    assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
 
-      if (BytesPerReg == 2) {
-        Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
-                                                          : AVR::sub_lo);
-      }
+    unsigned RegIdx = ByteNumber / BytesPerReg;
+    if (RegIdx >= NumOpRegs)
+      return true;
+    Reg = MI->getOperand(OpNum + RegIdx).getReg();
 
-      O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
-      return false;
+    if (BytesPerReg == 2) {
+      Reg = TRI.getSubReg(Reg,
+                          ByteNumber % BytesPerReg ? AVR::sub_hi : AVR::sub_lo);
     }
-  }
 
-  // Print global symbols.
-  const auto &MO = MI->getOperand(OpNum);
-  if (Error && MO.getType() == MachineOperand::MO_GlobalAddress) {
-    PrintSymbolOperand(MO, O);
+    O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
     return false;
   }
 
-  if (Error)
-    printOperand(MI, OpNum, O);
+  if (MO.getType() == MachineOperand::MO_GlobalAddress)
+    PrintSymbolOperand(MO, O); // Print global symbols.
+  else
+    printOperand(MI, OpNum, O); // Fallback to ordinary cases.
 
   return false;
 }
@@ -259,9 +254,9 @@ bool AVRAsmPrinter::doFinalization(Module &M) {
     auto *Section = cast<MCSectionELF>(TLOF.SectionForGlobal(&GO, TM));
     if (Section->getName().startswith(".data"))
       NeedsCopyData = true;
-    else if (Section->getName().startswith(".rodata") && SubTM->hasPROGMEM())
-      // AVRs that have a separate PROGMEM (that's most AVRs) store .rodata
-      // sections in RAM.
+    else if (Section->getName().startswith(".rodata") && SubTM->hasLPM())
+      // AVRs that have a separate program memory (that's most AVRs) store
+      // .rodata sections in RAM.
       NeedsCopyData = true;
     else if (Section->getName().startswith(".bss"))
       NeedsClearBSS = true;

llvm/lib/Target/AVR/AVRDevices.td

@@ -65,11 +65,6 @@ def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
                                    "The device supports the 16-bit MOVW "
                                    "instruction">;
 
-// The device has a separate flash namespace that must be accessed using special
-// instructions like lpm.
-def FeaturePROGMEM : SubtargetFeature<"progmem", "m_hasPROGMEM", "true",
-                                      "The device has a separate flash namespace">;
-
 // The device supports the `LPM` instruction, with implied destination being r0.
 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
                                   "The device supports the `LPM` instruction">;
@@ -125,6 +120,12 @@ def FeatureTinyEncoding
                        "The device has Tiny core specific "
                        "instruction encodings">;
 
+// When writing a 16-bit port or storing a 16-bit word, do the low byte first.
+def FeatureLowByteFirst
+    : SubtargetFeature<"lowbytefirst", "m_hasLowByteFirst", "true",
+                       "Do the low byte first when writing a 16-bit port or "
+                       "storing a 16-bit word">;
+
 // The device has CPU registers mapped in data address space
 def FeatureMMR : SubtargetFeature<"memmappedregs", "m_hasMemMappedGPR", "true",
                                   "The device has CPU registers "
@@ -161,7 +162,7 @@ def ELFArchXMEGA7 : ELFArch<"EF_AVR_ARCH_XMEGA7">;
 // device should have.
 def FamilyAVR0 : Family<"avr0", []>;
 
-def FamilyAVR1 : Family<"avr1", [FamilyAVR0, FeatureLPM, FeaturePROGMEM, FeatureMMR]>;
+def FamilyAVR1 : Family<"avr1", [FamilyAVR0, FeatureLPM, FeatureMMR]>;
 
 def FamilyAVR2
     : Family<"avr2",
@@ -197,17 +198,18 @@ def FamilyTiny
               FeatureSmallStack]>;
 
 def FamilyXMEGA3 : Family<"xmega3",
-                          [FamilyAVR0, FeatureLPM, FeaturePROGMEM, FeatureIJMPCALL,
+                          [FamilyAVR0, FeatureLPM, FeatureIJMPCALL,
                            FeatureADDSUBIW, FeatureSRAM, FeatureJMPCALL,
                            FeatureMultiplication, FeatureMOVW, FeatureLPMX,
-                           FeatureBREAK]>;
+                           FeatureBREAK, FeatureLowByteFirst]>;
 
 def FamilyXMEGA : Family<"xmega",
-                         [FamilyAVR0, FeatureLPM, FeaturePROGMEM, FeatureIJMPCALL,
+                         [FamilyAVR0, FeatureLPM, FeatureIJMPCALL,
                           FeatureADDSUBIW, FeatureSRAM, FeatureJMPCALL,
                           FeatureMultiplication, FeatureMOVW, FeatureLPMX,
                           FeatureSPM, FeatureBREAK, FeatureEIJMPCALL,
-                          FeatureSPMX, FeatureDES, FeatureELPM, FeatureELPMX]>;
+                          FeatureSPMX, FeatureDES, FeatureELPM, FeatureELPMX,
+                          FeatureLowByteFirst]>;
 
 def FamilyXMEGAU : Family<"xmegau", [FamilyXMEGA, FeatureRMW]>;