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[X86][SchedModels] Fix missing ReadAdvance for MULX and ADCX/ADOX (PR51494)
Before this patch, instructions MULX32rm and MULX64rm were missing a ReadAdvance for the implicit read of register EDX/RDX. This patch fixes the issue, and it also introduces a new SchedWrite for the two variants of MULX. The general idea behind this last change is to eventually decrease the number of InstRW in the scheduling models. This patch also adds a ReadAdvance for the implicit read of EFLAGS in ADCX/ADOX. Differential Revision: https://reviews.llvm.org/D108372
1 parent 5cf5df8 commit 35d4292

20 files changed

+137
-144
lines changed

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1502,8 +1502,12 @@ let hasSideEffects = 0 in {
15021502
let mayLoad = 1 in
15031503
def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
15041504
!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1505-
1506-
[]>, T8XD, VEX_4V, Sched<[sched.Folded, WriteIMulH]>;
1505+
[]>, T8XD, VEX_4V,
1506+
Sched<[sched.Folded, WriteIMulH,
1507+
// Memory operand.
1508+
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
1509+
// Implicit read of EDX/RDX
1510+
sched.ReadAfterFold]>;
15071511

15081512
// Pseudo instructions to be used when the low result isn't used. The
15091513
// instruction is defined to keep the high if both destinations are the same.
@@ -1518,9 +1522,9 @@ let hasSideEffects = 0 in {
15181522

15191523
let Predicates = [HasBMI2] in {
15201524
let Uses = [EDX] in
1521-
defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteIMul32>;
1525+
defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteMULX32>;
15221526
let Uses = [RDX] in
1523-
defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteIMul64>, VEX_W;
1527+
defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, VEX_W;
15241528
}
15251529

15261530
//===----------------------------------------------------------------------===//
@@ -1547,7 +1551,12 @@ let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
15471551
"adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
15481552
} // SchedRW
15491553

1550-
let mayLoad = 1, SchedRW = [WriteADC.Folded, WriteADC.ReadAfterFold] in {
1554+
let mayLoad = 1,
1555+
SchedRW = [WriteADC.Folded, WriteADC.ReadAfterFold,
1556+
// Memory operand.
1557+
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
1558+
// Implicit read of EFLAGS
1559+
WriteADC.ReadAfterFold] in {
15511560
def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
15521561
(ins GR32:$src1, i32mem:$src2),
15531562
"adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;

‎llvm/lib/Target/X86/X86SchedBroadwell.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,9 +123,11 @@ defm : X86WriteRes<WriteIMul16Imm, [BWPort1,BWPort0156], 4, [1,1], 2>;
123123
defm : X86WriteRes<WriteIMul16ImmLd, [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>;
124124
defm : BWWriteResPair<WriteIMul16Reg, [BWPort1], 3>;
125125
defm : BWWriteResPair<WriteIMul32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
126+
defm : BWWriteResPair<WriteMULX32, [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
126127
defm : BWWriteResPair<WriteIMul32Imm, [BWPort1], 3>;
127128
defm : BWWriteResPair<WriteIMul32Reg, [BWPort1], 3>;
128129
defm : BWWriteResPair<WriteIMul64, [BWPort1,BWPort5], 4, [1,1], 2>;
130+
defm : BWWriteResPair<WriteMULX64, [BWPort1,BWPort5], 4, [1,1], 2>;
129131
defm : BWWriteResPair<WriteIMul64Imm, [BWPort1], 3>;
130132
defm : BWWriteResPair<WriteIMul64Reg, [BWPort1], 3>;
131133
def : WriteRes<WriteIMulH, []> { let Latency = 3; }

‎llvm/lib/Target/X86/X86SchedHaswell.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,9 +140,11 @@ defm : X86WriteRes<WriteIMul16Imm, [HWPort1,HWPort0156], 4, [1,1], 2>;
140140
defm : X86WriteRes<WriteIMul16ImmLd, [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>;
141141
defm : HWWriteResPair<WriteIMul16Reg, [HWPort1], 3>;
142142
defm : HWWriteResPair<WriteIMul32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;
143+
defm : HWWriteResPair<WriteMULX32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;
143144
defm : HWWriteResPair<WriteIMul32Imm, [HWPort1], 3>;
144145
defm : HWWriteResPair<WriteIMul32Reg, [HWPort1], 3>;
145146
defm : HWWriteResPair<WriteIMul64, [HWPort1,HWPort6], 4, [1,1], 2>;
147+
defm : HWWriteResPair<WriteMULX64, [HWPort1,HWPort6], 4, [1,1], 2>;
146148
defm : HWWriteResPair<WriteIMul64Imm, [HWPort1], 3>;
147149
defm : HWWriteResPair<WriteIMul64Reg, [HWPort1], 3>;
148150
def : WriteRes<WriteIMulH, []> { let Latency = 3; }

‎llvm/lib/Target/X86/X86SchedSandyBridge.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,9 +124,11 @@ defm : X86WriteRes<WriteIMul16Imm, [SBPort1,SBPort015], 4, [1,1], 2>;
124124
defm : X86WriteRes<WriteIMul16ImmLd, [SBPort1,SBPort015,SBPort23], 8, [1,1,1], 3>;
125125
defm : SBWriteResPair<WriteIMul16Reg, [SBPort1], 3>;
126126
defm : SBWriteResPair<WriteIMul32, [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>;
127+
defm : SBWriteResPair<WriteMULX32, [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>;
127128
defm : SBWriteResPair<WriteIMul32Imm, [SBPort1], 3>;
128129
defm : SBWriteResPair<WriteIMul32Reg, [SBPort1], 3>;
129130
defm : SBWriteResPair<WriteIMul64, [SBPort1,SBPort0], 4, [1,1], 2>;
131+
defm : SBWriteResPair<WriteMULX64, [SBPort1,SBPort0], 4, [1,1], 2>;
130132
defm : SBWriteResPair<WriteIMul64Imm, [SBPort1], 3>;
131133
defm : SBWriteResPair<WriteIMul64Reg, [SBPort1], 3>;
132134
def : WriteRes<WriteIMulH, []> { let Latency = 3; }

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,9 +122,11 @@ defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>;
122122
defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
123123
defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>;
124124
defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
125+
defm : SKLWriteResPair<WriteMULX32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
125126
defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>;
126127
defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>;
127128
defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>;
129+
defm : SKLWriteResPair<WriteMULX64, [SKLPort1,SKLPort5], 4, [1,1], 2>;
128130
defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>;
129131
defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>;
130132
def : WriteRes<WriteIMulH, []> { let Latency = 3; }

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,9 +123,11 @@ defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1
123123
defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>;
124124
defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
125125
defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
126+
defm : SKXWriteResPair<WriteMULX32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
126127
defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>;
127128
defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>;
128129
defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>;
130+
defm : SKXWriteResPair<WriteMULX64, [SKXPort1,SKXPort5], 4, [1,1], 2>;
129131
defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>;
130132
defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>;
131133
def : WriteRes<WriteIMulH, []> { let Latency = 3; }

‎llvm/lib/Target/X86/X86Schedule.td

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,9 @@ defm WriteIMul32Reg : X86SchedWritePair; // Integer 32-bit multiplication by reg
148148
defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication.
149149
defm WriteIMul64Imm : X86SchedWritePair; // Integer 64-bit multiplication by immediate.
150150
defm WriteIMul64Reg : X86SchedWritePair; // Integer 64-bit multiplication by register.
151-
def WriteIMulH : SchedWrite; // Integer multiplication, high part.
151+
defm WriteMULX32 : X86SchedWritePair; // Integer 32-bit Multiplication without affecting flags.
152+
defm WriteMULX64 : X86SchedWritePair; // Integer 64-bit Multiplication without affecting flags.
153+
def WriteIMulH : SchedWrite; // Integer multiplication, high part (only used by MULX).
152154

153155
def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.
154156
def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.

‎llvm/lib/Target/X86/X86ScheduleAtom.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,8 @@ defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12]
9191
defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>;
9292
defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
9393
defm : X86WriteResUnsupported<WriteIMulH>;
94+
defm : X86WriteResPairUnsupported<WriteMULX32>;
95+
defm : X86WriteResPairUnsupported<WriteMULX64>;
9496

9597
defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>;
9698
defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>;

‎llvm/lib/Target/X86/X86ScheduleBdVer2.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -435,7 +435,11 @@ defm : PdWriteResExPair<WriteIMul32Reg, [PdEX1, PdMul], 4, [1, 2]>;
435435
defm : PdWriteResExPair<WriteIMul64, [PdEX1, PdMul], 6, [1, 6]>;
436436
defm : PdWriteResExPair<WriteIMul64Imm, [PdEX1, PdMul], 6, [1, 4],1, 1>;
437437
defm : PdWriteResExPair<WriteIMul64Reg, [PdEX1, PdMul], 6, [1, 4]>;
438-
defm : X86WriteResUnsupported<WriteIMulH>; // BMI2 MULX
438+
439+
// BMI2 MULX
440+
defm : X86WriteResUnsupported<WriteIMulH>;
441+
defm : X86WriteResPairUnsupported<WriteMULX32>;
442+
defm : X86WriteResPairUnsupported<WriteMULX64>;
439443

440444
defm : PdWriteResExPair<WriteDiv8, [PdEX1, PdDiv], 12, [1, 12]>;
441445
defm : PdWriteResExPair<WriteDiv16, [PdEX1, PdDiv], 15, [1, 15], 2>;

‎llvm/lib/Target/X86/X86ScheduleBtVer2.td

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -209,7 +209,9 @@ defm : JWriteResIntPair<WriteIMul32Reg, [JALU1, JMul], 3, [1, 1], 1>;
209209
defm : JWriteResIntPair<WriteIMul64, [JALU1, JMul], 6, [1, 4], 2>;
210210
defm : JWriteResIntPair<WriteIMul64Imm, [JALU1, JMul], 6, [1, 4], 1>;
211211
defm : JWriteResIntPair<WriteIMul64Reg, [JALU1, JMul], 6, [1, 4], 1>;
212-
defm : X86WriteRes<WriteIMulH, [JALU1], 6, [4], 1>;
212+
defm : X86WriteResUnsupported<WriteIMulH>;
213+
defm : X86WriteResPairUnsupported<WriteMULX32>;
214+
defm : X86WriteResPairUnsupported<WriteMULX64>;
213215

214216
defm : JWriteResIntPair<WriteDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
215217
defm : JWriteResIntPair<WriteDiv16, [JALU1, JDiv], 17, [1, 17], 2>;

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