x86, riscv64: mark constructors as unsafe

Author: newAM

CHANGELOG.md

@@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Added a changelog.
 - Added support for 32-bit ARM architectures ([#33]).
+- Changed `X86::new` and `RISCV64::new` to unsafe.
 
 [#33]: https://github.com/rust-embedded/qemu-exit/pull/33
 

README.md

@@ -21,12 +21,12 @@ let qemu_exit_handle = qemu_exit::AArch64::new();
 
 // addr: The address of sifive_test.
 #[cfg(target_arch = "riscv64")]
-let qemu_exit_handle = qemu_exit::RISCV64::new(addr);
+let qemu_exit_handle = unsafe { qemu_exit::RISCV64::new(addr) };
 
 // io_base:             I/O-base of isa-debug-exit.
 // custom_exit_success: A custom success code; Must be an odd number.
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-let qemu_exit_handle = qemu_exit::X86::new(io_base, custom_exit_success);
+let qemu_exit_handle = unsafe { qemu_exit::X86::new(io_base, custom_exit_success) };
 
 qemu_exit_handle.exit(1337);
 qemu_exit_handle.exit_success();
@@ -38,6 +38,7 @@ qemu_exit_handle.exit_failure();
 ### AArch64/AArch32
 
 Pass the `-semihosting` argument to the QEMU invocation, e.g.:
+
 ```
 qemu-system-aarch64 -M raspi3 -serial stdio -semihosting -kernel kernel8.img
 qemu-system-arm -nographic -M mps2-an500 -cpu cortex-m7 -serial mon:stdio -semihosting -kernel
@@ -47,13 +48,15 @@ kernel.img
 ### RISCV64
 
 You need to chose a machine with the `sifive_test` device, for exemple `-M virt`:
+
 ```
 qemu-system-riscv64 -M virt -nographic -monitor none -serial stdio -kernel kernel.elf
 ```
 
 ### x86/x86_64
 
 Add the special ISA debug exit device by passing the flags:
+
 ```
 -device isa-debug-exit,iobase=0xf4,iosize=0x04
 ```
@@ -67,14 +70,15 @@ binary-OR'ed with `0x1`. This is hardcoded and therefore, with `isa-debug-exit`,
 possible to let QEMU invoke `exit(0)`.
 
 ```rust
-let qemu_exit_handle = qemu_exit::X86::new(io_base, custom_exit_success);
+let qemu_exit_handle = unsafe { qemu_exit::X86::new(io_base, custom_exit_success) };
 ```
 
 #### x86/x86_64 Linux
 
 To use this mechanism from Linux userspace, the kernel must be compiled with
 `CONFIG_X86_IOPL_IOPERM=y` (which is the default) and the process must start with root privileges
 (or `CAP_SYS_RAWIO`) and call: [`ioperm(2)`](https://man7.org/linux/man-pages/man2/ioperm.2.html):
+
 ```rust
 nix::errno::Errno::result(unsafe { libc::ioperm( 0xf4, 4, 1 )}).expect("ioperm failed");
 ```

src/lib.rs

@@ -20,12 +20,12 @@
 //!
 //! // addr: The address of sifive_test.
 //! #[cfg(target_arch = "riscv64")]
-//! let qemu_exit_handle = qemu_exit::RISCV64::new(addr);
+//! let qemu_exit_handle = unsafe { qemu_exit::RISCV64::new(addr) };
 //!
 //! // io_base:             I/O-base of isa-debug-exit.
 //! // custom_exit_success: A custom success code; Must be an odd number.
 //! #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-//! let qemu_exit_handle = qemu_exit::X86::new(io_base, custom_exit_success);
+//! let qemu_exit_handle = unsafe { qemu_exit::X86::new(io_base, custom_exit_success) };
 //!
 //! qemu_exit_handle.exit(1337);
 //! qemu_exit_handle.exit_success();
@@ -74,7 +74,7 @@
 //! possible to let QEMU invoke `exit(0)`.
 //!
 //! ```ignore
-//! let qemu_exit_handle = qemu_exit::X86::new(io_base, custom_exit_success);
+//! let qemu_exit_handle = unsafe { qemu_exit::X86::new(io_base, custom_exit_success) };
 //! ```
 //!
 //! ## Literature

src/riscv64.rs

@@ -26,7 +26,7 @@ const fn exit_code_encode(code: u32) -> u32 {
 
 impl RISCV64 {
     /// Create an instance.
-    pub const fn new(addr: u64) -> Self {
+    pub const unsafe fn new(addr: u64) -> Self {
         RISCV64 { addr }
     }
 }

src/x86.rs

@@ -33,7 +33,7 @@ fn outl(io_base: u16, code: u32) {
 
 impl X86 {
     /// Create an instance.
-    pub const fn new(io_base: u16, custom_exit_success: u32) -> Self {
+    pub const unsafe fn new(io_base: u16, custom_exit_success: u32) -> Self {
         assert!((custom_exit_success & 1) == 1);
 
         X86 {

tests/exit_13.rs

@@ -35,7 +35,7 @@ mod armv7m_mps2an500;
 //--------------------------------------------------------------------------------------------------
 
 #[cfg(target_arch = "riscv64")]
-const QEMU_EXIT_HANDLE: qemu_exit::RISCV64 = qemu_exit::RISCV64::new(0x100000);
+const QEMU_EXIT_HANDLE: qemu_exit::RISCV64 = unsafe { qemu_exit::RISCV64::new(0x100000) };
 
 #[cfg(target_arch = "riscv64")]
 mod riscv64_virt;
@@ -45,7 +45,7 @@ mod riscv64_virt;
 //--------------------------------------------------------------------------------------------------
 
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-const QEMU_EXIT_HANDLE: qemu_exit::X86 = qemu_exit::X86::new(0xf4, 5);
+const QEMU_EXIT_HANDLE: qemu_exit::X86 = unsafe { qemu_exit::X86::new(0xf4, 5) };
 
 //--------------------------------------------------------------------------------------------------
 // Generic code