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SCB.ICSR is more than 8 bits #314

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Dirbaio opened this issue Feb 25, 2021 · 1 comment
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SCB.ICSR is more than 8 bits #314

Dirbaio opened this issue Feb 25, 2021 · 1 comment
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@Dirbaio
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Dirbaio commented Feb 25, 2021

This code here reads ICSR and casts it to 8 bits. In cortex-m3 it is more than 8 bits because there can be up to 480 interrupts.

let irqn = unsafe { core::ptr::read(SCB_ICSR) as u8 as i16 - 16 };

This is the same as rust-embedded/cortex-m#332

bors bot added a commit that referenced this issue Mar 2, 2021
315: Use volatile read for ICSR register r=adamgreig a=lulf

This prevents the compiler from optimizing the read.

Edit: I also added a change to include the 9th bit in the IRQ. I can leave that out if it would break anything. 

#314

Co-authored-by: Ulf Lilleengen <[email protected]>
bors bot added a commit that referenced this issue Mar 2, 2021
315: Use volatile read for ICSR register r=adamgreig a=lulf

This prevents the compiler from optimizing the read.

Edit: I also added a change to include the 9th bit in the IRQ. I can leave that out if it would break anything. 

#314

Co-authored-by: Ulf Lilleengen <[email protected]>
@adamgreig
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Closed by #315.

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