Move EL2 MPU registers to bitfields

Author: korken89

cortex-ar/src/register/armv8r/hmpuir.rs

@@ -3,7 +3,13 @@
 use crate::register::{SysReg, SysRegRead};
 
 /// HMPUIR (*Hyp MPU Type Register*)
-pub struct Hmpuir(pub u32);
+#[bitbybit::bitfield(u32)]
+pub struct Hmpuir {
+    /// The number of EL2 MPU regions implemented
+    #[bits(0..=7, r)]
+    region: u8,
+}
+
 impl SysReg for Hmpuir {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -16,6 +22,6 @@ impl Hmpuir {
     #[inline]
     /// Reads HMPUIR (*Hyp MPU Type Register*)
     pub fn read() -> Hmpuir {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }

cortex-ar/src/register/armv8r/hprbar.rs

@@ -1,9 +1,54 @@
 //! Code for managing HPRBAR (*Hyp Protection Region Base Address Register*)
 
+use arbitrary_int::u26;
+
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
+/// Shareability for an MPU Region
+#[derive(Debug, PartialEq, Eq)]
+#[bitbybit::bitenum(u2, exhaustive = true)]
+pub enum Shareability {
+    /// Non-shareable
+    NonShareable = 0b00,
+    /// Reserved
+    Reserved = 0b01,
+    /// Outer-Shareable
+    OuterShareable = 0b10,
+    /// Inner-Shareable
+    InnerShareable = 0b11,
+}
+
+/// Access Permissions for an MPU Region
+#[derive(Debug, PartialEq, Eq)]
+#[bitbybit::bitenum(u2, exhaustive = true)]
+pub enum AccessPerms {
+    /// Read-Write at EL2, No access at EL1/0
+    ReadWriteNoEL10 = 0b00,
+    /// Read-Write at EL2, EL1, and EL0
+    ReadWrite = 0b01,
+    /// Read-Only at EL2, No access at EL1/0
+    ReadOnlyNoEL10 = 0b10,
+    /// Read-Only at EL2, EL1, and EL0
+    ReadOnly = 0b11,
+}
+
 /// HPRBAR (*Hyp Protection Region Base Address Register*)
-pub struct Hprbar(pub u32);
+#[bitbybit::bitfield(u32)]
+pub struct Hprbar {
+    /// Base Address
+    #[bits(6..=31, rw)]
+    base: u26,
+    /// Shareability
+    #[bits(3..=4, rw)]
+    shareability: Shareability,
+    /// Access Permissions
+    #[bits(1..=2, rw)]
+    access_perms: AccessPerms,
+    /// Execute Never
+    #[bits(0..=0, rw)]
+    nx: bool,
+}
+
 impl SysReg for Hprbar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -16,20 +61,16 @@ impl Hprbar {
     #[inline]
     /// Reads HPRBAR (*Hyp Protection Region Base Address Register*)
     pub fn read() -> Hprbar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 impl crate::register::SysRegWrite for Hprbar {}
 impl Hprbar {
     #[inline]
     /// Writes HPRBAR (*Hyp Protection Region Base Address Register*)
-    ///
-    /// # Safety
-    ///
-    /// Ensure that this value is appropriate for this register
-    pub unsafe fn write(value: Self) {
+    pub fn write(value: Self) {
         unsafe {
-            <Self as SysRegWrite>::write_raw(value.0);
+            <Self as SysRegWrite>::write_raw(value.raw_value());
         }
     }
 }

cortex-ar/src/register/armv8r/hprlar.rs

@@ -1,9 +1,23 @@
 //! Code for managing HPRLAR (*Hyp Protection Region Limit Address Register*)
 
+use arbitrary_int::{u26, u3};
+
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HPRLAR (*Hyp Protection Region Limit Address Register*)
-pub struct Hprlar(pub u32);
+#[bitbybit::bitfield(u32)]
+pub struct Hprlar {
+    /// Length of region
+    #[bits(6..=31, rw)]
+    limit: u26,
+    /// Which HMAIR attribute to use
+    #[bits(1..=3, rw)]
+    mair: u3,
+    /// Is region enabled?
+    #[bits(0..=0, rw)]
+    enabled: bool,
+}
+
 impl SysReg for Hprlar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -16,20 +30,16 @@ impl Hprlar {
     #[inline]
     /// Reads HPRLAR (*Hyp Protection Region Limit Address Register*)
     pub fn read() -> Hprlar {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 impl crate::register::SysRegWrite for Hprlar {}
 impl Hprlar {
     #[inline]
     /// Writes HPRLAR (*Hyp Protection Region Limit Address Register*)
-    ///
-    /// # Safety
-    ///
-    /// Ensure that this value is appropriate for this register
-    pub unsafe fn write(value: Self) {
+    pub fn write(value: Self) {
         unsafe {
-            <Self as SysRegWrite>::write_raw(value.0);
+            <Self as SysRegWrite>::write_raw(value.raw_value());
         }
     }
 }

cortex-ar/src/register/armv8r/hprselr.rs

@@ -24,10 +24,8 @@ impl Hprselr {
     #[inline]
     /// Writes HPRSELR (*Hyp Protection Region Selection Register*)
     ///
-    /// # Safety
-    ///
-    /// Ensure that this value is appropriate for this register
-    pub unsafe fn write(value: Self) {
+    /// Controls what appears in HPRLAR and HPRBAR
+    pub fn write(value: Self) {
         unsafe {
             <Self as SysRegWrite>::write_raw(value.0);
         }

cortex-ar/src/register/armv8r/hsctlr.rs

@@ -3,7 +3,46 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HSCTLR (*Hyp System Control Register*)
-pub struct Hsctlr(pub u32);
+#[bitbybit::bitfield(u32)]
+pub struct Hsctlr {
+    /// T32 Exception Enable. Controls whether exceptions to EL2 are taken to A32 or T32 state
+    #[bits(30..=30, rw)]
+    te: bool,
+    /// Exception Endianness. The value of the PSTATE.E bit on entry to Hyp mode
+    #[bits(25..=25, rw)]
+    ee: bool,
+    /// Fast Interrupts enable
+    #[bits(21..=21, rw)]
+    fi: bool,
+    /// Write permission implies XN (Execute-never)
+    #[bits(19..=19, rw)]
+    wxn: bool,
+    /// Background Region enable for EL2
+    #[bits(17..=17, rw)]
+    br: bool,
+    /// Instruction access Cacheability control, for accesses at EL2
+    #[bits(12..=12, rw)]
+    i: bool,
+    /// SETEND instruction disable. Disables SETEND instructions at EL2
+    #[bits(8..=8, rw)]
+    sed: bool,
+    /// IT Disable. Disables some uses of IT instructions at EL2
+    #[bits(7..=7, rw)]
+    itd: bool,
+    /// System instruction memory barrier enable
+    #[bits(5..=5, rw)]
+    cp15ben: bool,
+    /// Cacheability control, for data accesses at EL2
+    #[bits(2..=2, rw)]
+    c: bool,
+    /// Alignment check enable
+    #[bits(1..=1, rw)]
+    a: bool,
+    /// MPU enable for the EL2 MPU
+    #[bits(0..=0, rw)]
+    m: bool,
+}
+
 impl SysReg for Hsctlr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -16,20 +55,26 @@ impl Hsctlr {
     #[inline]
     /// Reads HSCTLR (*Hyp System Control Register*)
     pub fn read() -> Hsctlr {
-        unsafe { Self(<Self as SysRegRead>::read_raw()) }
+        unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 impl crate::register::SysRegWrite for Hsctlr {}
 impl Hsctlr {
     #[inline]
     /// Writes HSCTLR (*Hyp System Control Register*)
-    ///
-    /// # Safety
-    ///
-    /// Ensure that this value is appropriate for this register
-    pub unsafe fn write(value: Self) {
+    pub fn write(value: Self) {
         unsafe {
-            <Self as SysRegWrite>::write_raw(value.0);
+            <Self as SysRegWrite>::write_raw(value.raw_value());
         }
     }
+    /// Read-modify-write this register
+    #[inline]
+    pub fn modify<F>(f: F)
+    where
+        F: FnOnce(&mut Self),
+    {
+        let mut val = Self::read();
+        f(&mut val);
+        Self::write(val);
+    }
 }