init

Author: ZR233

Cargo.lock

@@ -15,7 +15,7 @@ members = [
     "platforms/axplat-riscv64-qemu-virt",
     "platforms/axplat-loongarch64-qemu-virt",
 
-    "examples/hello-kernel",
+    "examples/hello-kernel", "platforms/axplat-aarch64-dyn",
 ]
 
 [workspace.package]

Cargo.toml

@@ -0,0 +1,14 @@
+[package]
+authors.workspace = true
+documentation.workspace = true
+edition.workspace = true
+homepage.workspace = true
+license.workspace = true
+name = "axplat-aarch64-dyn"
+repository.workspace = true
+version = "0.1.0"
+
+[dependencies]
+axconfig-macros = "0.2"
+axplat = {git = "https://github.com/arceos-org/axplat_crates"}
+pie-boot = {version = "0.1.11"}

platforms/axplat-aarch64-dyn/Cargo.toml

@@ -0,0 +1,47 @@
+# Architecture identifier.
+arch = "aarch64"                        # str
+# Platform identifier.
+platform = "aarch64-dyn"                # str
+# Platform package.
+package = "axplat-aarch64-dyn"          # str
+
+#
+# Platform configs
+#
+[plat]
+# Platform family (deprecated).
+family = "" # str
+# Number of CPUs.
+cpu-num = 256                                   # uint
+# No need.
+phys-memory-base = 0                            # uint
+# No need.
+phys-memory-size = 0x0                          # uint
+# No need.
+kernel-base-paddr = 0x0                         # uint
+# Base virtual address of the kernel image.
+kernel-base-vaddr = "0xffff_8000_0000_0000"     # uint
+# No need.
+phys-virt-offset = "0"      # uint
+# Offset of bus address and phys address. some boards, the bus address is
+# different from the physical address.
+phys-bus-offset = 0                             # uint
+# Kernel address space base.
+kernel-aspace-base = "0xffff_8000_0000_0000"    # uint
+# Kernel address space size.
+kernel-aspace-size = "0x0000_7fff_ffff_f000"    # uint
+
+#
+# Device specifications
+#
+[devices]
+# MMIO regions with format (`base_paddr`, `size`).
+mmio-regions = []           # [(uint, uint)]
+# VirtIO MMIO regions with format (`base_paddr`, `size`).
+virtio-mmio-regions = []    # [(uint, uint)]
+# Base physical address of the PCIe ECAM space.
+pci-ecam-base = 0           # uint
+# End PCI bus number.
+pci-bus-end = 0             # uint
+# PCI device memory ranges.
+pci-ranges = []             # [(uint, uint)]

platforms/axplat-aarch64-dyn/axconfig.toml

@@ -0,0 +1,22 @@
+fn main() {
+    println!("cargo:rerun-if-env-changed=AX_CONFIG_PATH");
+    if let Ok(config_path) = std::env::var("AX_CONFIG_PATH") {
+        println!("cargo:rerun-if-changed={config_path}");
+    }
+
+    println!("cargo:rustc-link-search={}", out_dir().display());
+    println!("cargo::rustc-link-arg=-Tlink.x");
+    println!("cargo::rustc-link-arg=-no-pie");
+    println!("cargo::rustc-link-arg=-znostart-stop-gc");
+
+    let script = "link.ld";
+
+    println!("cargo:rerun-if-changed={script}");
+    let ld_content = std::fs::read_to_string(script).unwrap();
+
+    std::fs::write(out_dir().join("link.x"), ld_content).expect("link.x write failed");
+}
+
+fn out_dir() -> PathBuf {
+    PathBuf::from(std::env::var("OUT_DIR").unwrap())
+}

platforms/axplat-aarch64-dyn/build.rs

@@ -0,0 +1,105 @@
+OUTPUT_ARCH(aarch64)
+
+__SMP = 4;
+
+INCLUDE "pie_boot.x"
+
+ENTRY(_start)
+SECTIONS
+{
+    _skernel = .;
+
+    .text : ALIGN(4K) {
+        _stext = .;
+        *(.text.boot)
+        *(.text .text.*)
+        . = ALIGN(4K);
+        _etext = .;
+    }
+
+    _srodata = .;
+    .rodata : ALIGN(4K) {
+        *(.rodata .rodata.*)
+        *(.srodata .srodata.*)
+        *(.sdata2 .sdata2.*)
+    }
+
+    .init_array : ALIGN(0x10) {
+        __init_array_start = .;
+        *(.init_array .init_array.*)
+        __init_array_end = .;
+    }
+
+    . = ALIGN(4K);
+    _erodata = .;
+
+    .data : ALIGN(4K) {
+        _sdata = .;
+        *(.data.boot_page_table)
+        . = ALIGN(4K);
+        *(.data .data.*)
+        *(.sdata .sdata.*)
+        *(.got .got.*)
+    }
+
+    .tdata : ALIGN(0x10) {
+        _stdata = .;
+        *(.tdata .tdata.*)
+        _etdata = .;
+    }
+
+    .tbss : ALIGN(0x10) {
+        _stbss = .;
+        *(.tbss .tbss.*)
+        *(.tcommon)
+        _etbss = .;
+    }
+
+    . = ALIGN(4K);
+    _percpu_start = .;
+    _percpu_end = _percpu_start + SIZEOF(.percpu);
+    .percpu 0x0 : AT(_percpu_start) {
+        _percpu_load_start = .;
+        *(.percpu .percpu.*)
+        _percpu_load_end = .;
+        . = _percpu_load_start + ALIGN(64) * __SMP;
+    }
+    . = _percpu_end;
+
+    . = ALIGN(4K);
+    _edata = .;
+
+    .bss : AT(.) ALIGN(4K) {
+        boot_stack = .;
+        *(.bss.stack)
+        . = ALIGN(4K);
+        boot_stack_top = .;
+
+        _sbss = .;
+        *(.bss .bss.*)
+        *(.sbss .sbss.*)
+        *(COMMON)
+        . = ALIGN(4K);
+        _ebss = .;
+    }
+
+    _ekernel = .;
+
+	/DISCARD/ : {
+        *(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
+    }
+}
+
+SECTIONS {
+    linkme_IRQ : { *(linkme_IRQ) }
+    linkm2_IRQ : { *(linkm2_IRQ) }
+    linkme_PAGE_FAULT : { *(linkme_PAGE_FAULT) }
+    linkm2_PAGE_FAULT : { *(linkm2_PAGE_FAULT) }
+    linkme_SYSCALL : { *(linkme_SYSCALL) }
+    linkm2_SYSCALL : { *(linkm2_SYSCALL) }
+    axns_resource : { *(axns_resource) }
+}
+INSERT AFTER .tbss;
+
+__kernel_load_end = _etdata;
+__kernel_code_end = _ekernel;

platforms/axplat-aarch64-dyn/link.ld

@@ -0,0 +1,18 @@
+use axplat::console::ConsoleIf;
+
+struct ConsoleIfImpl;
+
+#[impl_plat_interface]
+impl ConsoleIf for ConsoleIfImpl {
+    /// Writes given bytes to the console.
+    fn write_bytes(bytes: &[u8]) {
+        todo!()
+    }
+
+    /// Reads bytes from the console into the given mutable slice.
+    ///
+    /// Returns the number of bytes read.
+    fn read_bytes(bytes: &mut [u8]) -> usize {
+        todo!()
+    }
+}

platforms/axplat-aarch64-dyn/src/console.rs

@@ -0,0 +1,76 @@
+use axplat::init::InitIf;
+
+struct InitIfImpl;
+
+#[impl_plat_interface]
+impl InitIf for InitIfImpl {
+    /// Initializes the platform at the early stage for the primary core.
+    ///
+    /// This function should be called immediately after the kernel has booted,
+    /// and performed earliest platform configuration and initialization (e.g.,
+    /// early console, clocking).
+    ///
+    /// # Arguments
+    ///
+    /// * `cpu_id` is the logical CPU ID (0, 1, ..., N-1, N is the number of CPU
+    /// cores on the platform).
+    /// * `arg` is passed from the bootloader (typically the device tree blob
+    /// address).
+    ///
+    /// # Before calling this function
+    ///
+    /// * CPU is booted in the kernel mode.
+    /// * Early page table is set up, virtual memory is enabled.
+    /// * CPU-local data is initialized.
+    ///
+    /// # After calling this function
+    ///
+    /// * Exception & interrupt handlers are set up.
+    /// * Early console is initialized.
+    /// * Current monotonic time and wall time can be obtained.
+    fn init_early(cpu_id: usize, arg: usize) {
+        todo!()
+    }
+
+    /// Initializes the platform at the early stage for secondary cores.
+    ///
+    /// See [`init_early`] for details.
+    fn init_early_secondary(cpu_id: usize) {
+        todo!()
+    }
+
+    /// Initializes the platform at the later stage for the primary core.
+    ///
+    /// This function should be called after the kernel has done part of its
+    /// initialization (e.g, logging, memory management), and finalized the rest of
+    /// platform configuration and initialization.
+    ///
+    /// # Arguments
+    ///
+    /// * `cpu_id` is the logical CPU ID (0, 1, ..., N-1, N is the number of CPU
+    /// cores on the platform).
+    /// * `arg` is passed from the bootloader (typically the device tree blob
+    /// address).
+    ///
+    /// # Before calling this function
+    ///
+    /// * Kernel logging is initialized.
+    /// * Fine-grained kernel page table is set up (if applicable).
+    /// * Physical memory allocation is initialized (if applicable).
+    ///
+    /// # After calling this function
+    ///
+    /// * Interrupt controller is initialized (if applicable).
+    /// * Timer interrupts are enabled (if applicable).
+    /// * Other platform devices are initialized.
+    fn init_later(cpu_id: usize, arg: usize) {
+        todo!()
+    }
+
+    /// Initializes the platform at the later stage for secondary cores.
+    ///
+    /// See [`init_later`] for details.
+    fn init_later_secondary(cpu_id: usize) {
+        todo!()
+    }
+}

platforms/axplat-aarch64-dyn/src/init.rs

@@ -0,0 +1,36 @@
+use axplat::irq::{IrqHandler, IrqIf};
+
+struct IrqIfImpl;
+
+#[impl_plat_interface]
+impl IrqIf for IrqIfImpl {
+    /// Enables or disables the given IRQ.
+    fn set_enable(irq: usize, enabled: bool) {
+        todo!()
+    }
+
+    /// Registers an IRQ handler for the given IRQ.
+    ///
+    /// It also enables the IRQ if the registration succeeds. It returns `false`
+    /// if the registration failed.
+    fn register(irq: usize, handler: IrqHandler) -> bool {
+        todo!()
+    }
+
+    /// Unregisters the IRQ handler for the given IRQ.
+    ///
+    /// It also disables the IRQ if the unregistration succeeds. It returns the
+    /// existing handler if it is registered, `None` otherwise.
+    fn unregister(irq: usize) -> Option<IrqHandler> {
+        todo!()
+    }
+
+    /// Handles the IRQ.
+    ///
+    /// It is called by the common interrupt handler. It should look up in the
+    /// IRQ handler table and calls the corresponding handler. If necessary, it
+    /// also acknowledges the interrupt controller after handling.
+    fn handle(irq: usize) {
+        todo!()
+    }
+}

platforms/axplat-aarch64-dyn/src/irq.rs

@@ -0,0 +1,24 @@
+#![cfg(all(target_arch = "aarch64", target_os = "none"))]
+#![no_std]
+
+#[macro_use]
+extern crate axplat;
+
+use pie_boot::BootArgs;
+
+mod console;
+mod init;
+mod irq;
+mod mem;
+mod power;
+mod time;
+
+mod config {
+    axconfig_macros::include_configs!(path_env = "AX_CONFIG_PATH", fallback = "axconfig.toml");
+}
+
+#[pie_boot::entry]
+fn main(_args: &BootArgs) -> ! {
+    // TODO: Implement actual bootstrap logic
+    axplat::call_main(0, 0);
+}