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drm/vc4: Disable the 2pixel/clock odd timings workaround for interlaced
Whilst BCM2712 does fix using odd horizontal timings, it doesn't work with interlaced modes. Drop the workaround for interlaced modes and revert to the same behaviour as BCM2711. #6281 Signed-off-by: Dave Stevenson <[email protected]>
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+30
-4
lines changed

4 files changed

+30
-4
lines changed

‎drivers/gpu/drm/vc4/vc4_crtc.c‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -361,7 +361,9 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
361361
bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
362362
bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
363363
u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
364-
u8 ppc = pv_data->pixels_per_clock;
364+
u8 ppc = (mode->flags & DRM_MODE_FLAG_INTERLACE) ?
365+
pv_data->pixels_per_clock_int :
366+
pv_data->pixels_per_clock;
365367

366368
u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
367369
u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
@@ -426,7 +428,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
426428
*/
427429
CRTC_WRITE(PV_V_CONTROL,
428430
PV_VCONTROL_CONTINUOUS |
429-
(vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |
431+
(vc4->gen >= VC4_GEN_6_C && ppc == 1 ?
432+
PV_VCONTROL_ODD_TIMING : 0) |
430433
(is_dsi ? PV_VCONTROL_DSI : 0) |
431434
PV_VCONTROL_INTERLACE |
432435
(odd_field_first
@@ -438,7 +441,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
438441
} else {
439442
CRTC_WRITE(PV_V_CONTROL,
440443
PV_VCONTROL_CONTINUOUS |
441-
(vc4->gen >= VC4_GEN_6_C ? PV_VCONTROL_ODD_TIMING : 0) |
444+
(vc4->gen >= VC4_GEN_6_C && ppc == 1 ?
445+
PV_VCONTROL_ODD_TIMING : 0) |
442446
(is_dsi ? PV_VCONTROL_DSI : 0));
443447
CRTC_WRITE(PV_VSYNCD_EVEN, 0);
444448
}
@@ -1205,6 +1209,7 @@ const struct vc4_pv_data bcm2835_pv0_data = {
12051209
},
12061210
.fifo_depth = 64,
12071211
.pixels_per_clock = 1,
1212+
.pixels_per_clock_int = 1,
12081213
.encoder_types = {
12091214
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
12101215
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
@@ -1220,6 +1225,7 @@ const struct vc4_pv_data bcm2835_pv1_data = {
12201225
},
12211226
.fifo_depth = 64,
12221227
.pixels_per_clock = 1,
1228+
.pixels_per_clock_int = 1,
12231229
.encoder_types = {
12241230
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
12251231
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
@@ -1235,6 +1241,7 @@ const struct vc4_pv_data bcm2835_pv2_data = {
12351241
},
12361242
.fifo_depth = 64,
12371243
.pixels_per_clock = 1,
1244+
.pixels_per_clock_int = 1,
12381245
.encoder_types = {
12391246
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
12401247
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
@@ -1250,6 +1257,7 @@ const struct vc4_pv_data bcm2711_pv0_data = {
12501257
},
12511258
.fifo_depth = 64,
12521259
.pixels_per_clock = 1,
1260+
.pixels_per_clock_int = 1,
12531261
.encoder_types = {
12541262
[0] = VC4_ENCODER_TYPE_DSI0,
12551263
[1] = VC4_ENCODER_TYPE_DPI,
@@ -1265,6 +1273,7 @@ const struct vc4_pv_data bcm2711_pv1_data = {
12651273
},
12661274
.fifo_depth = 64,
12671275
.pixels_per_clock = 1,
1276+
.pixels_per_clock_int = 1,
12681277
.encoder_types = {
12691278
[0] = VC4_ENCODER_TYPE_DSI1,
12701279
[1] = VC4_ENCODER_TYPE_SMI,
@@ -1280,6 +1289,7 @@ const struct vc4_pv_data bcm2711_pv2_data = {
12801289
},
12811290
.fifo_depth = 256,
12821291
.pixels_per_clock = 2,
1292+
.pixels_per_clock_int = 2,
12831293
.encoder_types = {
12841294
[0] = VC4_ENCODER_TYPE_HDMI0,
12851295
},
@@ -1294,6 +1304,7 @@ const struct vc4_pv_data bcm2711_pv3_data = {
12941304
},
12951305
.fifo_depth = 64,
12961306
.pixels_per_clock = 1,
1307+
.pixels_per_clock_int = 1,
12971308
.encoder_types = {
12981309
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
12991310
},
@@ -1308,6 +1319,7 @@ const struct vc4_pv_data bcm2711_pv4_data = {
13081319
},
13091320
.fifo_depth = 64,
13101321
.pixels_per_clock = 2,
1322+
.pixels_per_clock_int = 2,
13111323
.encoder_types = {
13121324
[0] = VC4_ENCODER_TYPE_HDMI1,
13131325
},
@@ -1321,6 +1333,7 @@ const struct vc4_pv_data bcm2712_pv0_data = {
13211333
},
13221334
.fifo_depth = 64,
13231335
.pixels_per_clock = 1,
1336+
.pixels_per_clock_int = 2,
13241337
.encoder_types = {
13251338
[0] = VC4_ENCODER_TYPE_HDMI0,
13261339
},
@@ -1334,6 +1347,7 @@ const struct vc4_pv_data bcm2712_pv1_data = {
13341347
},
13351348
.fifo_depth = 64,
13361349
.pixels_per_clock = 1,
1350+
.pixels_per_clock_int = 2,
13371351
.encoder_types = {
13381352
[0] = VC4_ENCODER_TYPE_HDMI1,
13391353
},

‎drivers/gpu/drm/vc4/vc4_drv.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -547,6 +547,8 @@ struct vc4_pv_data {
547547

548548
/* Number of pixels output per clock period */
549549
u8 pixels_per_clock;
550+
/* Number of pixels output per clock period when in an interlaced mode */
551+
u8 pixels_per_clock_int;
550552

551553
enum vc4_encoder_type encoder_types[4];
552554
};

‎drivers/gpu/drm/vc4/vc4_hdmi.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1704,7 +1704,9 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
17041704
unsigned long long tmds_char_rate = mode->clock * 1000;
17051705
unsigned long long tmds_bit_rate;
17061706

1707-
if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1707+
if (vc4_hdmi->variant->unsupported_odd_h_timings ||
1708+
(vc4_hdmi->variant->unsupported_int_odd_h_timings &&
1709+
(mode->flags & DRM_MODE_FLAG_INTERLACE))) {
17081710
if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
17091711
/* Only try to fixup DBLCLK modes to get 480i and 576i
17101712
* working.
@@ -3341,6 +3343,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
33413343
PHY_LANE_CK,
33423344
},
33433345
.unsupported_odd_h_timings = true,
3346+
.unsupported_int_odd_h_timings = true,
33443347
.external_irq_controller = true,
33453348

33463349
.init_resources = vc5_hdmi_init_resources,
@@ -3370,6 +3373,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
33703373
PHY_LANE_2,
33713374
},
33723375
.unsupported_odd_h_timings = true,
3376+
.unsupported_int_odd_h_timings = true,
33733377
.external_irq_controller = true,
33743378

33753379
.init_resources = vc5_hdmi_init_resources,
@@ -3399,6 +3403,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
33993403
PHY_LANE_CK,
34003404
},
34013405
.unsupported_odd_h_timings = false,
3406+
.unsupported_int_odd_h_timings = true,
34023407
.external_irq_controller = true,
34033408

34043409
.init_resources = vc5_hdmi_init_resources,
@@ -3426,6 +3431,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
34263431
PHY_LANE_CK,
34273432
},
34283433
.unsupported_odd_h_timings = false,
3434+
.unsupported_int_odd_h_timings = true,
34293435
.external_irq_controller = true,
34303436

34313437
.init_resources = vc5_hdmi_init_resources,

‎drivers/gpu/drm/vc4/vc4_hdmi.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,10 @@ struct vc4_hdmi_variant {
4747

4848
/* The BCM2711 cannot deal with odd horizontal pixel timings */
4949
bool unsupported_odd_h_timings;
50+
/* The BCM2712 can handle odd horizontal pixel timings, but not in
51+
* interlaced modes
52+
*/
53+
bool unsupported_int_odd_h_timings;
5054

5155
/*
5256
* The BCM2711 CEC/hotplug IRQ controller is shared between the

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