Address various warnings as errors (#8581)

Summary:
Pull Request resolved: #8581

Some projects uses more restrictive build options than currently used in ET CI.

This means we encountered a number of errors when enabling for a microcontroller.

Reviewed By: digantdesai, swolchok

Differential Revision: D69139962

Author: JakeStevens

extension/threadpool/cpuinfo_utils.cpp

@@ -6,6 +6,7 @@
  * LICENSE file in the root directory of this source tree.
  */
 
+#include <c10/util/irange.h>
 #include <executorch/extension/threadpool/cpuinfo_utils.h>
 
 #include <fstream>
@@ -84,7 +85,7 @@ bool populate_available_cpu_mids() {
   cpu_midrs->resize(num_possible_cores);
   const std::string kMidrFilePathPrefix = "/sys/devices/system/cpu/cpu";
   const std::string kMidrFilePathSuffix = "/regs/identification/midr_el1";
-  for (int32_t i = 0; i < num_possible_cores; ++i) {
+  for (const auto i : c10::irange(num_possible_cores)) {
     std::string midr_file_path =
         kMidrFilePathPrefix + std::to_string(i) + kMidrFilePathSuffix;
     ET_LOG(Info, "Reading file %s", midr_file_path.c_str());
@@ -115,7 +116,7 @@ uint32_t _get_num_performant_cores() {
     ET_LOG(Info, "CPU info and manual query on # of cpus dont match.");
     return 0;
   }
-  for (int32_t i = 0; i < cpu_midrs->size(); ++i) {
+  for (const auto i : c10::irange(cpu_midrs->size())) {
     uint32_t masked_midr = (*cpu_midrs)[i] & RIVISION_MASK;
     switch (masked_midr) {
       case CPUINFO_ARM_MIDR_CORTEX_A520:
@@ -148,7 +149,7 @@ uint32_t get_num_performant_cores() {
   uint32_t num_possible_cores = cpuinfo_get_processors_count();
   uint32_t num_non_performant_core = 0;
   if (uarch_count > 1) {
-    for (int32_t i = 0; i < uarch_count; ++i) {
+    for (const auto i : c10::irange(uarch_count)) {
       const struct cpuinfo_uarch_info* uarch_info = cpuinfo_get_uarch(i);
       if (is_non_performant_core(uarch_info)) {
         num_non_performant_core += uarch_info->processor_count;

extension/threadpool/targets.bzl

@@ -23,6 +23,7 @@ def define_common_targets():
         srcs = _THREADPOOL_SRCS,
         deps = [
             "//executorch/runtime/core:core",
+            "//executorch/runtime/core/portable_type/c10/c10:c10",
         ],
         exported_headers = _THREADPOOL_HEADERS,
         exported_deps = [

kernels/portable/cpu/op__to_dim_order_copy.cpp

@@ -6,6 +6,8 @@
  * LICENSE file in the root directory of this source tree.
  */
 
+#include <c10/util/irange.h>
+
 #include <executorch/kernels/portable/cpu/scalar_utils.h>
 #include <executorch/kernels/portable/cpu/util/copy_ops_util.h>
 #include <executorch/runtime/core/exec_aten/util/dim_order_util.h>
@@ -41,7 +43,7 @@ int64_t coordinateToIndexWithDimOrder(
 
   dim_order_to_stride_nocheck(
       sizes.data(), dim_order.data(), sizes.size(), strides);
-  for (size_t i = 0; i < self.dim(); ++i) {
+  for (const auto i : c10::irange(self.dim())) {
     index += cur_indices[i] * strides[i];
   }
   return index;
@@ -59,7 +61,7 @@ void _to_dim_order_copy_impl(const Tensor& self, Tensor& out) {
   for (ssize_t i = 0; i < self.numel(); i++) {
     // Update the current indices.
     for (ssize_t j = self.dim() - 1; j >= 0; j--) {
-      if (coordinate[j] + 1 < self.size(j)) {
+      if (coordinate[j] + 1 < static_cast<size_t>(self.size(j))) {
         coordinate[j]++;
         break;
       } else {

kernels/portable/cpu/op_amax.cpp

@@ -6,6 +6,7 @@
  * LICENSE file in the root directory of this source tree.
  */
 
+#include <c10/util/irange.h>
 #include <cmath>
 
 #include <executorch/kernels/portable/cpu/util/reduce_util.h>
@@ -44,7 +45,7 @@ Tensor& amax_out(
 
   ET_SWITCH_REALHBBF16_TYPES(in.scalar_type(), ctx, "amax.out", CTYPE, [&]() {
     CTYPE* out_data = out.mutable_data_ptr<CTYPE>();
-    for (size_t out_ix = 0; out_ix < out.numel(); ++out_ix) {
+    for (const auto out_ix : c10::irange(out.numel())) {
       out_data[out_ix] = reduce_over_dim_list<CTYPE>(
           [](CTYPE v, CTYPE max_v) {
             return std::isnan(v) || v > max_v ? v : max_v;

kernels/portable/cpu/op_amin.cpp

@@ -5,7 +5,7 @@
  * This source code is licensed under the BSD-style license found in the
  * LICENSE file in the root directory of this source tree.
  */
-
+#include <c10/util/irange.h>
 #include <cmath>
 
 #include <executorch/kernels/portable/cpu/util/reduce_util.h>
@@ -44,7 +44,7 @@ Tensor& amin_out(
 
   ET_SWITCH_REALHBBF16_TYPES(in.scalar_type(), ctx, "amin.out", CTYPE, [&]() {
     CTYPE* out_data = out.mutable_data_ptr<CTYPE>();
-    for (size_t out_ix = 0; out_ix < out.numel(); ++out_ix) {
+    for (const auto out_ix : c10::irange(out.numel())) {
       out_data[out_ix] = reduce_over_dim_list<CTYPE>(
           [](CTYPE v, CTYPE min_v) {
             return std::isnan(v) || v < min_v ? v : min_v;

kernels/portable/cpu/op_argmax.cpp

@@ -6,6 +6,7 @@
  * LICENSE file in the root directory of this source tree.
  */
 
+#include <c10/util/irange.h>
 #include <cmath>
 #include <tuple>
 
@@ -46,7 +47,7 @@ Tensor& argmax_out(
   ET_SWITCH_REALHBF16_TYPES(in.scalar_type(), ctx, "argmax.out", CTYPE, [&] {
     long* out_data = out.mutable_data_ptr<long>();
 
-    for (size_t out_ix = 0; out_ix < out.numel(); ++out_ix) {
+    for (const auto out_ix : c10::irange(out.numel())) {
       std::tuple<CTYPE, long> acc = reduce_over_dim<CTYPE>(
           [](CTYPE v, long ix, CTYPE acc_val, long acc_ix) {
             if (!std::isnan(acc_val) && (std::isnan(v) || v > acc_val)) {

kernels/portable/cpu/op_argmin.cpp

@@ -6,6 +6,7 @@
  * LICENSE file in the root directory of this source tree.
  */
 
+#include <c10/util/irange.h>
 #include <cmath>
 #include <tuple>
 
@@ -46,7 +47,7 @@ Tensor& argmin_out(
   ET_SWITCH_REALHBF16_TYPES(in.scalar_type(), ctx, "argmin.out", CTYPE, [&] {
     long* out_data = out.mutable_data_ptr<long>();
 
-    for (size_t out_ix = 0; out_ix < out.numel(); ++out_ix) {
+    for (const auto out_ix : c10::irange(out.numel())) {
       std::tuple<CTYPE, long> acc = reduce_over_dim<CTYPE>(
           [](CTYPE v, long ix, CTYPE acc_val, long acc_ix) {
             if (!std::isnan(acc_val) && (std::isnan(v) || v < acc_val)) {

kernels/portable/cpu/op_expand_copy.cpp

@@ -96,7 +96,8 @@ Tensor& expand_copy_out(
 
   ET_KERNEL_CHECK(
       ctx,
-      repeat_tensor(self, {repeats, repeats_size}, out) == Error::Ok,
+      repeat_tensor(self, makeArrayRef(repeats, repeats_size), out) ==
+          Error::Ok,
       InvalidArgument,
       out);
 

kernels/portable/cpu/util/activation_ops_util.cpp

@@ -31,7 +31,7 @@ bool check_glu_args(const Tensor& in, int64_t dim, Tensor& out) {
   ET_LOG_AND_RETURN_IF_FALSE(tensor_is_floating_type(in));
 
   const size_t non_negative_dim = dim < 0 ? dim + in.dim() : dim;
-  const size_t dim_size = in.size(non_negative_dim);
+  const ssize_t dim_size = in.size(non_negative_dim);
 
   ET_CHECK_OR_RETURN_FALSE(
       dim_size % 2 == 0,

kernels/portable/cpu/util/broadcast_util.cpp

@@ -6,6 +6,7 @@
  * LICENSE file in the root directory of this source tree.
  */
 
+#include <executorch/kernels/portable/cpu/util/broadcast_util.h>
 #include <executorch/kernels/portable/cpu/util/repeat_util.h>
 #include <executorch/runtime/core/exec_aten/exec_aten.h>
 #include <executorch/runtime/core/exec_aten/util/scalar_type_util.h>
@@ -274,7 +275,7 @@ void delinearize_index(
     size_t* out_indexes,
     const size_t out_indexes_len) {
   ET_CHECK(shape.size() <= out_indexes_len);
-  for (auto i = 0; i < shape.size(); ++i) {
+  for (size_t i = 0; i < shape.size(); ++i) {
     auto dim = shape.size() - 1 - i;
     auto dim_size = shape[dim];
     out_indexes[dim] = linear_index % dim_size;
@@ -304,7 +305,8 @@ size_t linearize_access_indexes(
   size_t linear_index = 0;
   for (size_t i = 0; i < indexes_broadcast_from.size(); ++i) {
     // If this dimension is broadcasted, add zero to the linear address.
-    if (indexes_broadcast_from[i] >= broadcast_from_shape[i]) {
+    if (indexes_broadcast_from[i] >=
+        static_cast<size_t>(broadcast_from_shape[i])) {
       ET_CHECK_MSG(
           broadcast_from_shape[i] == 1,
           "Expected dim size == 1 if broadcasted, but actual dim size is %zu",