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Arm backend: Convert asserts to raise errors in op_mul (#10134)
Asserts are converted to proper raises to ensure graph integrity. Improve error message. Signed-off-by: Sebastian Larsson <[email protected]> Co-authored-by: Oscar Andersson <[email protected]>
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backends/arm/operators/op_mul.py

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,15 @@ def define_node(
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inputs: List[TosaArg],
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output: TosaArg,
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) -> None:
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assert inputs[0].dtype == inputs[1].dtype == output.dtype == ts.DType.INT8
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if (
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inputs[0].dtype != ts.DType.INT8
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or inputs[1].dtype != ts.DType.INT8
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or output.dtype != ts.DType.INT8
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):
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raise ValueError(
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f"Inputs and output for {self.target} need to be INT8, got "
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f"{inputs[0].dtype=}, {inputs[1].dtype=} and {output.dtype=}"
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)
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dim_order = (
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inputs[0].dim_order

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