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Revert "[InstCombine] Extend foldICmpBinOp to add-like or. (rust-lang#71… (llvm#76167)
…396)" This reverts commit 8773c9b.
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-126
lines changed

2 files changed

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-126
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‎llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp‎

Lines changed: 29 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -4624,35 +4624,27 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
46244624
}
46254625

46264626
bool NoOp0WrapProblem = false, NoOp1WrapProblem = false;
4627-
bool Op0HasNUW = false, Op1HasNUW = false;
4628-
bool Op0HasNSW = false, Op1HasNSW = false;
4627+
if (BO0 && isa<OverflowingBinaryOperator>(BO0))
4628+
NoOp0WrapProblem =
4629+
ICmpInst::isEquality(Pred) ||
4630+
(CmpInst::isUnsigned(Pred) && BO0->hasNoUnsignedWrap()) ||
4631+
(CmpInst::isSigned(Pred) && BO0->hasNoSignedWrap());
4632+
if (BO1 && isa<OverflowingBinaryOperator>(BO1))
4633+
NoOp1WrapProblem =
4634+
ICmpInst::isEquality(Pred) ||
4635+
(CmpInst::isUnsigned(Pred) && BO1->hasNoUnsignedWrap()) ||
4636+
(CmpInst::isSigned(Pred) && BO1->hasNoSignedWrap());
4637+
46294638
// Analyze the case when either Op0 or Op1 is an add instruction.
46304639
// Op0 = A + B (or A and B are null); Op1 = C + D (or C and D are null).
4631-
auto hasNoWrapProblem = [](const BinaryOperator &BO, CmpInst::Predicate Pred,
4632-
bool &HasNSW, bool &HasNUW) -> bool {
4633-
if (isa<OverflowingBinaryOperator>(BO)) {
4634-
HasNUW = BO.hasNoUnsignedWrap();
4635-
HasNSW = BO.hasNoSignedWrap();
4636-
return ICmpInst::isEquality(Pred) ||
4637-
(CmpInst::isUnsigned(Pred) && HasNUW) ||
4638-
(CmpInst::isSigned(Pred) && HasNSW);
4639-
} else if (BO.getOpcode() == Instruction::Or) {
4640-
HasNUW = true;
4641-
HasNSW = true;
4642-
return true;
4643-
} else {
4644-
return false;
4645-
}
4646-
};
46474640
Value *A = nullptr, *B = nullptr, *C = nullptr, *D = nullptr;
4648-
4649-
if (BO0) {
4650-
match(BO0, m_AddLike(m_Value(A), m_Value(B)));
4651-
NoOp0WrapProblem = hasNoWrapProblem(*BO0, Pred, Op0HasNSW, Op0HasNUW);
4641+
if (BO0 && BO0->getOpcode() == Instruction::Add) {
4642+
A = BO0->getOperand(0);
4643+
B = BO0->getOperand(1);
46524644
}
4653-
if (BO1) {
4654-
match(BO1, m_AddLike(m_Value(C), m_Value(D)));
4655-
NoOp1WrapProblem = hasNoWrapProblem(*BO1, Pred, Op1HasNSW, Op1HasNUW);
4645+
if (BO1 && BO1->getOpcode() == Instruction::Add) {
4646+
C = BO1->getOperand(0);
4647+
D = BO1->getOperand(1);
46564648
}
46574649

46584650
// icmp (A+B), A -> icmp B, 0 for equalities or if there is no overflow.
@@ -4772,15 +4764,17 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
47724764
APInt AP2Abs = AP2->abs();
47734765
if (AP1Abs.uge(AP2Abs)) {
47744766
APInt Diff = *AP1 - *AP2;
4767+
bool HasNUW = BO0->hasNoUnsignedWrap() && Diff.ule(*AP1);
4768+
bool HasNSW = BO0->hasNoSignedWrap();
47754769
Constant *C3 = Constant::getIntegerValue(BO0->getType(), Diff);
4776-
Value *NewAdd = Builder.CreateAdd(
4777-
A, C3, "", Op0HasNUW && Diff.ule(*AP1), Op0HasNSW);
4770+
Value *NewAdd = Builder.CreateAdd(A, C3, "", HasNUW, HasNSW);
47784771
return new ICmpInst(Pred, NewAdd, C);
47794772
} else {
47804773
APInt Diff = *AP2 - *AP1;
4774+
bool HasNUW = BO1->hasNoUnsignedWrap() && Diff.ule(*AP2);
4775+
bool HasNSW = BO1->hasNoSignedWrap();
47814776
Constant *C3 = Constant::getIntegerValue(BO0->getType(), Diff);
4782-
Value *NewAdd = Builder.CreateAdd(
4783-
C, C3, "", Op1HasNUW && Diff.ule(*AP1), Op1HasNSW);
4777+
Value *NewAdd = Builder.CreateAdd(C, C3, "", HasNUW, HasNSW);
47844778
return new ICmpInst(Pred, A, NewAdd);
47854779
}
47864780
}
@@ -4874,14 +4868,16 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
48744868
isKnownNonZero(Z, Q.DL, /*Depth=*/0, Q.AC, Q.CxtI, Q.DT);
48754869
// if Z != 0 and nsw(X * Z) and nsw(Y * Z)
48764870
// X * Z eq/ne Y * Z -> X eq/ne Y
4877-
if (NonZero && BO0 && BO1 && Op0HasNSW && Op1HasNSW)
4871+
if (NonZero && BO0 && BO1 && BO0->hasNoSignedWrap() &&
4872+
BO1->hasNoSignedWrap())
48784873
return new ICmpInst(Pred, X, Y);
48794874
} else
48804875
NonZero = isKnownNonZero(Z, Q.DL, /*Depth=*/0, Q.AC, Q.CxtI, Q.DT);
48814876

48824877
// If Z != 0 and nuw(X * Z) and nuw(Y * Z)
48834878
// X * Z u{lt/le/gt/ge}/eq/ne Y * Z -> X u{lt/le/gt/ge}/eq/ne Y
4884-
if (NonZero && BO0 && BO1 && Op0HasNUW && Op1HasNUW)
4879+
if (NonZero && BO0 && BO1 && BO0->hasNoUnsignedWrap() &&
4880+
BO1->hasNoUnsignedWrap())
48854881
return new ICmpInst(Pred, X, Y);
48864882
}
48874883
}
@@ -4980,8 +4976,8 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
49804976
return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0));
49814977

49824978
case Instruction::Shl: {
4983-
bool NUW = Op0HasNUW && Op1HasNUW;
4984-
bool NSW = Op0HasNSW && Op1HasNSW;
4979+
bool NUW = BO0->hasNoUnsignedWrap() && BO1->hasNoUnsignedWrap();
4980+
bool NSW = BO0->hasNoSignedWrap() && BO1->hasNoSignedWrap();
49854981
if (!NUW && !NSW)
49864982
break;
49874983
if (!NSW && I.isSigned())

‎llvm/test/Transforms/InstCombine/icmp.ll‎

Lines changed: 24 additions & 93 deletions
Original file line numberDiff line numberDiff line change
@@ -3862,9 +3862,10 @@ define <8 x i1> @bitreverse_vec_ne(<8 x i16> %x, <8 x i16> %y) {
38623862
define i1 @knownbits1(i8 %a, i8 %b) {
38633863
; CHECK-LABEL: @knownbits1(
38643864
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3865+
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
38653866
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3866-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3867-
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A1]], [[TMP1]]
3867+
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3868+
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A2]], [[B2]]
38683869
; CHECK-NEXT: ret i1 [[C]]
38693870
;
38703871
%a1 = and i8 %a, 5
@@ -3878,9 +3879,10 @@ define i1 @knownbits1(i8 %a, i8 %b) {
38783879
define i1 @knownbits2(i8 %a, i8 %b) {
38793880
; CHECK-LABEL: @knownbits2(
38803881
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3882+
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
38813883
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3882-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3883-
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A1]], [[TMP1]]
3884+
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3885+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A2]], [[B2]]
38843886
; CHECK-NEXT: ret i1 [[C]]
38853887
;
38863888
%a1 = and i8 %a, 5
@@ -3894,9 +3896,10 @@ define i1 @knownbits2(i8 %a, i8 %b) {
38943896
define i1 @knownbits3(i8 %a, i8 %b) {
38953897
; CHECK-LABEL: @knownbits3(
38963898
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1
3899+
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
38973900
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3898-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3899-
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[TMP1]], [[A1]]
3901+
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3902+
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B2]], [[A2]]
39003903
; CHECK-NEXT: ret i1 [[C]]
39013904
;
39023905
%a1 = and i8 %a, 5
@@ -3910,9 +3913,10 @@ define i1 @knownbits3(i8 %a, i8 %b) {
39103913
define <2 x i1> @knownbits4(<2 x i8> %a, <2 x i8> %b) {
39113914
; CHECK-LABEL: @knownbits4(
39123915
; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], <i8 1, i8 1>
3916+
; CHECK-NEXT: [[A2:%.*]] = or disjoint <2 x i8> [[A1]], <i8 4, i8 4>
39133917
; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], <i8 2, i8 2>
3914-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint <2 x i8> [[B1]], <i8 1, i8 1>
3915-
; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[TMP1]], [[A1]]
3918+
; CHECK-NEXT: [[B2:%.*]] = or disjoint <2 x i8> [[B1]], <i8 5, i8 5>
3919+
; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[B2]], [[A2]]
39163920
; CHECK-NEXT: ret <2 x i1> [[C]]
39173921
;
39183922
%a1 = and <2 x i8> %a, <i8 5, i8 5>
@@ -3928,9 +3932,10 @@ define <2 x i1> @knownbits4(<2 x i8> %a, <2 x i8> %b) {
39283932
define i1 @knownbits5(i8 %a, i8 %b) {
39293933
; CHECK-LABEL: @knownbits5(
39303934
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
3935+
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
39313936
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3932-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3933-
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A1]], [[TMP1]]
3937+
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3938+
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A2]], [[B2]]
39343939
; CHECK-NEXT: ret i1 [[C]]
39353940
;
39363941
%a1 = and i8 %a, 133
@@ -3944,9 +3949,10 @@ define i1 @knownbits5(i8 %a, i8 %b) {
39443949
define i1 @knownbits6(i8 %a, i8 %b) {
39453950
; CHECK-LABEL: @knownbits6(
39463951
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
3952+
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
39473953
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3948-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3949-
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A1]], [[TMP1]]
3954+
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3955+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A2]], [[B2]]
39503956
; CHECK-NEXT: ret i1 [[C]]
39513957
;
39523958
%a1 = and i8 %a, 133
@@ -3960,9 +3966,10 @@ define i1 @knownbits6(i8 %a, i8 %b) {
39603966
define <2 x i1> @knownbits7(<2 x i8> %a, <2 x i8> %b) {
39613967
; CHECK-LABEL: @knownbits7(
39623968
; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], <i8 -127, i8 -127>
3969+
; CHECK-NEXT: [[A2:%.*]] = or disjoint <2 x i8> [[A1]], <i8 4, i8 4>
39633970
; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], <i8 2, i8 2>
3964-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint <2 x i8> [[B1]], <i8 1, i8 1>
3965-
; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[TMP1]], [[A1]]
3971+
; CHECK-NEXT: [[B2:%.*]] = or disjoint <2 x i8> [[B1]], <i8 5, i8 5>
3972+
; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[B2]], [[A2]]
39663973
; CHECK-NEXT: ret <2 x i1> [[C]]
39673974
;
39683975
%a1 = and <2 x i8> %a, <i8 133, i8 133>
@@ -3976,9 +3983,10 @@ define <2 x i1> @knownbits7(<2 x i8> %a, <2 x i8> %b) {
39763983
define i1 @knownbits8(i8 %a, i8 %b) {
39773984
; CHECK-LABEL: @knownbits8(
39783985
; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127
3986+
; CHECK-NEXT: [[A2:%.*]] = or disjoint i8 [[A1]], 4
39793987
; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2
3980-
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1
3981-
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[TMP1]], [[A1]]
3988+
; CHECK-NEXT: [[B2:%.*]] = or disjoint i8 [[B1]], 5
3989+
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[B2]], [[A2]]
39823990
; CHECK-NEXT: ret i1 [[C]]
39833991
;
39843992
%a1 = and i8 %a, 133
@@ -4904,80 +4912,3 @@ define i1 @or_positive_sgt_zero_multi_use(i8 %a) {
49044912
%cmp = icmp sgt i8 %b, 0
49054913
ret i1 %cmp
49064914
}
4907-
4908-
4909-
define i1 @disjoint_or_sgt_1(i8 %a, i8 %b) {
4910-
; CHECK-LABEL: @disjoint_or_sgt_1(
4911-
; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B:%.*]], 2
4912-
; CHECK-NEXT: [[ICMP_:%.*]] = icmp sle i8 [[B1]], [[A:%.*]]
4913-
; CHECK-NEXT: ret i1 [[ICMP_]]
4914-
;
4915-
%a1 = or disjoint i8 %a, 1
4916-
%b1 = add nsw i8 %b, 2
4917-
%icmp_ = icmp sgt i8 %a1, %b1
4918-
ret i1 %icmp_
4919-
}
4920-
4921-
define i1 @disjoint_or_sgt_2(i8 %a, i8 %b) {
4922-
; CHECK-LABEL: @disjoint_or_sgt_2(
4923-
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
4924-
; CHECK-NEXT: [[B1:%.*]] = add i8 [[B:%.*]], 1
4925-
; CHECK-NEXT: [[ICMP_:%.*]] = icmp sgt i8 [[A1]], [[B1]]
4926-
; CHECK-NEXT: ret i1 [[ICMP_]]
4927-
;
4928-
%a1 = or disjoint i8 %a, 2
4929-
%b1 = add i8 %b, 1
4930-
%icmp_ = icmp sgt i8 %a1, %b1
4931-
ret i1 %icmp_
4932-
}
4933-
4934-
define i1 @disjoint_or_sgt_3(i8 %a, i8 %b) {
4935-
; CHECK-LABEL: @disjoint_or_sgt_3(
4936-
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
4937-
; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B:%.*]], 1
4938-
; CHECK-NEXT: [[ICMP_:%.*]] = icmp sgt i8 [[A1]], [[B1]]
4939-
; CHECK-NEXT: ret i1 [[ICMP_]]
4940-
;
4941-
%a1 = or disjoint i8 %a, 2
4942-
%b1 = add nuw i8 %b, 1
4943-
%icmp_ = icmp sgt i8 %a1, %b1
4944-
ret i1 %icmp_
4945-
}
4946-
4947-
define i1 @disjoint_or_ugt_1(i8 %a, i8 %b) {
4948-
; CHECK-LABEL: @disjoint_or_ugt_1(
4949-
; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B:%.*]], 2
4950-
; CHECK-NEXT: [[ICMP_:%.*]] = icmp ule i8 [[B1]], [[A:%.*]]
4951-
; CHECK-NEXT: ret i1 [[ICMP_]]
4952-
;
4953-
%a1 = or disjoint i8 %a, 1
4954-
%b1 = add nsw i8 %b, 2
4955-
%icmp_ = icmp ugt i8 %a1, %b1
4956-
ret i1 %icmp_
4957-
}
4958-
4959-
define i1 @disjoint_or_ugt_2(i8 %a, i8 %b) {
4960-
; CHECK-LABEL: @disjoint_or_ugt_2(
4961-
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
4962-
; CHECK-NEXT: [[B1:%.*]] = add i8 [[B:%.*]], 1
4963-
; CHECK-NEXT: [[ICMP_:%.*]] = icmp ugt i8 [[A1]], [[B1]]
4964-
; CHECK-NEXT: ret i1 [[ICMP_]]
4965-
;
4966-
%a1 = or disjoint i8 %a, 2
4967-
%b1 = add i8 %b, 1
4968-
%icmp_ = icmp ugt i8 %a1, %b1
4969-
ret i1 %icmp_
4970-
}
4971-
4972-
define i1 @disjoint_or_ugt_3(i8 %a, i8 %b) {
4973-
; CHECK-LABEL: @disjoint_or_ugt_3(
4974-
; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2
4975-
; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B:%.*]], 1
4976-
; CHECK-NEXT: [[ICMP_:%.*]] = icmp ugt i8 [[A1]], [[B1]]
4977-
; CHECK-NEXT: ret i1 [[ICMP_]]
4978-
;
4979-
%a1 = or disjoint i8 %a, 2
4980-
%b1 = add nuw i8 %b, 1
4981-
%icmp_ = icmp ugt i8 %a1, %b1
4982-
ret i1 %icmp_
4983-
}

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