drm/vc4: plane: Use dlist offset instead of pointer

The current code passes the dlist pointer to vc4_plane_write_dlist to
tell where in the dlist RAM to store the plane dlist content.

In order to ease later changes, let's move that direct pointer to a base
offset from the start of the dlist RAM.

Signed-off-by: Maxime Ripard <[email protected]>

Author: mripard

drivers/gpu/drm/vc4/vc4_drv.h

@@ -983,7 +983,10 @@ int vc4_kms_load(struct drm_device *dev);
 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 				 enum drm_plane_type type);
 int vc4_plane_create_additional_planes(struct drm_device *dev);
-u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
+u32 vc4_plane_write_dlist(struct vc4_hvs *hvs,
+			  struct vc4_crtc_state *vc4_crtc_state,
+			  struct vc4_plane_state *vc4_plane_state,
+			  unsigned dlist_offset);
 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
 void vc4_plane_async_set_fb(struct drm_plane *plane,
 			    struct drm_framebuffer *fb);

drivers/gpu/drm/vc4/vc4_hvs.c

@@ -677,14 +677,14 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
 									 crtc);
 	struct drm_device *dev = crtc->dev;
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
+	struct vc4_hvs *hvs = vc4->hvs;
 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 	unsigned int channel = vc4_state->assigned_channel;
 	struct drm_plane *plane;
-	struct vc4_plane_state *vc4_plane_state;
 	bool debug_dump_regs = false;
 	bool enable_bg_fill = false;
-	u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
-	u32 __iomem *dlist_next = dlist_start;
+	unsigned int dlist_start = vc4_state->mm.start;
+	unsigned int dlist_next = dlist_start;
 
 	if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 		return;
@@ -696,6 +696,9 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
 
 	/* Copy all the active planes' dlist contents to the hardware dlist. */
 	drm_atomic_crtc_for_each_plane(plane, crtc) {
+		struct vc4_plane_state *vc4_plane_state =
+			to_vc4_plane_state(plane->state);
+
 		/* Is this the first active plane? */
 		if (dlist_next == dlist_start) {
 			/* We need to enable background fill when a plane
@@ -706,14 +709,14 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
 			 * already needs it or all planes on top blend from
 			 * the first or a lower plane.
 			 */
-			vc4_plane_state = to_vc4_plane_state(plane->state);
 			enable_bg_fill = vc4_plane_state->needs_bg_fill;
 		}
 
-		dlist_next += vc4_plane_write_dlist(plane, dlist_next);
+		dlist_next += vc4_plane_write_dlist(hvs, vc4_state,
+						    vc4_plane_state, dlist_next);
 	}
 
-	writel(SCALER_CTL0_END, dlist_next);
+	writel(SCALER_CTL0_END, vc4->hvs->dlist + dlist_next);
 	dlist_next++;
 
 	WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);

drivers/gpu/drm/vc4/vc4_plane.c

@@ -1181,18 +1181,21 @@ static void vc4_plane_atomic_update(struct drm_plane *plane,
 	 */
 }
 
-u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
+u32 vc4_plane_write_dlist(struct vc4_hvs *hvs,
+			  struct vc4_crtc_state *vc4_crtc_state,
+			  struct vc4_plane_state *vc4_plane_state,
+			  unsigned dlist_offset)
 {
-	struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
+	u32 __iomem *dlist = hvs->dlist + dlist_offset;
 	int i;
 
-	vc4_state->hw_dlist = dlist;
+	vc4_plane_state->hw_dlist = dlist;
 
 	/* Can't memcpy_toio() because it needs to be 32-bit writes. */
-	for (i = 0; i < vc4_state->dlist_count; i++)
-		writel(vc4_state->dlist[i], &dlist[i]);
+	for (i = 0; i < vc4_plane_state->dlist_count; i++)
+		writel(vc4_plane_state->dlist[i], &dlist[i]);
 
-	return vc4_state->dlist_count;
+	return vc4_plane_state->dlist_count;
 }
 
 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)