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[RISCV] Use Root instead of N throughout the worklist loop in combineBinOp_VLToVWBinOp_VL. #99416

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Merged
merged 3 commits into from
Jul 18, 2024
Merged

[RISCV] Use Root instead of N throughout the worklist loop in combineBinOp_VLToVWBinOp_VL. #99416

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1939f35
[RISCV] Use Root instead of N throughout the worklist loop in combine…
topperc Jul 18, 2024
5f5cf22
[RISCV] Add additional test for combineBinOp_VLToVWBinOp_VL. NFC
topperc Jul 18, 2024
58ae802
Merge branch 'pr/binop-worklist'
topperc Jul 18, 2024
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10 changes: 5 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14998,8 +14998,8 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N,
if (!NodeExtensionHelper::isSupportedRoot(Root, Subtarget))
return SDValue();

NodeExtensionHelper LHS(N, 0, DAG, Subtarget);
NodeExtensionHelper RHS(N, 1, DAG, Subtarget);
NodeExtensionHelper LHS(Root, 0, DAG, Subtarget);
NodeExtensionHelper RHS(Root, 1, DAG, Subtarget);
auto AppendUsersIfNeeded = [&Worklist,
&Inserted](const NodeExtensionHelper &Op) {
if (Op.needToPromoteOtherUsers()) {
Expand All @@ -15016,18 +15016,18 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N,
return SDValue();

SmallVector<NodeExtensionHelper::CombineToTry> FoldingStrategies =
NodeExtensionHelper::getSupportedFoldings(N);
NodeExtensionHelper::getSupportedFoldings(Root);

assert(!FoldingStrategies.empty() && "Nothing to be folded");
bool Matched = false;
for (int Attempt = 0;
(Attempt != 1 + NodeExtensionHelper::isCommutative(N)) && !Matched;
(Attempt != 1 + NodeExtensionHelper::isCommutative(Root)) && !Matched;
++Attempt) {

for (NodeExtensionHelper::CombineToTry FoldingStrategy :
FoldingStrategies) {
std::optional<CombineResult> Res =
FoldingStrategy(N, LHS, RHS, DAG, Subtarget);
FoldingStrategy(Root, LHS, RHS, DAG, Subtarget);
if (Res) {
Matched = true;
CombinesToApply.push_back(*Res);
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38 changes: 38 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
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Expand Up @@ -882,3 +882,41 @@ define <2 x i64> @vwmul_vx_v2i64_i64(ptr %x, ptr %y) {
%g = mul <2 x i64> %e, %f
ret <2 x i64> %g
}

define <2 x i16> @vwmul_v2i16_multiuse(ptr %x, ptr %y, ptr %z, ptr %w) {
; CHECK-LABEL: vwmul_v2i16_multiuse:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vle8.v v9, (a2)
; CHECK-NEXT: vle8.v v10, (a3)
; CHECK-NEXT: vle8.v v11, (a0)
; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: vsext.vf2 v8, v9
; CHECK-NEXT: vsext.vf2 v9, v10
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vwmul.vv v13, v11, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmul.vv v9, v12, v9
; CHECK-NEXT: vdivu.vv v8, v12, v8
; CHECK-NEXT: vor.vv v9, v13, v9
; CHECK-NEXT: vor.vv v8, v9, v8
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
%b = load <2 x i8>, ptr %y
%c = load <2 x i8>, ptr %z
%d = load <2 x i8>, ptr %w

%as = sext <2 x i8> %a to <2 x i16>
%bs = sext <2 x i8> %b to <2 x i16>
%cs = sext <2 x i8> %c to <2 x i16>
%ds = sext <2 x i8> %d to <2 x i16>

%e = mul <2 x i16> %as, %ds
%f = mul <2 x i16> %bs, %ds ; shares 1 use with %e
%g = udiv <2 x i16> %bs, %cs ; shares 1 use with %f, and no uses with %e

%h = or <2 x i16> %e, %f
%i = or <2 x i16> %h, %g
ret <2 x i16> %i
}
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