[NVPTX] fix emission for i1 load and extload #99392
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@llvm/pr-subscribers-backend-nvptx Author: Meredith Julian (mjulian31) ChangesCurrently, an illegal 2-byte load from a 1-byte global variable is being generated. This change instead generates a 1-byte load and zero-extends it to i16 register. This was always the intended behavior of the function. In addition, an i1 ext load of any kind needs to be promoted. A missing setLoadExtAction for ISD::EXTLOAD was causing an "Unhandled source type" unreachable due to an illegal i1 ext load during ISelDAGtoDAG (see below bug). Bug #98033. LIT tests run locally:
Full diff: https://github.com/llvm/llvm-project/pull/99392.diff 3 Files Affected:
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index a2181b478c269..bc23998455a68 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -629,6 +629,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
setTruncStoreAction(VT, MVT::i1, Expand);
}
@@ -2920,9 +2921,10 @@ SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
assert(Node->getValueType(0) == MVT::i1 &&
"Custom lowering for i1 load only");
- SDValue newLD = DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
- LD->getPointerInfo(), LD->getAlign(),
- LD->getMemOperand()->getFlags());
+ SDValue newLD = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i16, LD->getChain(),
+ LD->getBasePtr(), LD->getPointerInfo(),
+ MVT::i8, LD->getAlign(),
+ LD->getMemOperand()->getFlags());
SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
// The legalizer (the caller) is expecting two values from the legalized
// load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
diff --git a/llvm/test/CodeGen/NVPTX/i1-ext-load.ll b/llvm/test/CodeGen/NVPTX/i1-ext-load.ll
new file mode 100644
index 0000000000000..b775e40470047
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/i1-ext-load.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function foo --extra_scrub --default-march nvptx64 --filter-out ".*//.*" --filter-out "[\{\}\(\)]" --version 5
+
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_50 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_50 | %ptxas-verify %}
+
+target triple = "nvptx-nvidia-cuda"
+
+define void @foo(ptr noalias readonly %ptr, ptr noalias %retval) {
+; CHECK-LABEL: foo(
+; CHECK: .reg .b16 %rs<2>;
+; CHECK: .reg .b32 %r<4>;
+; CHECK: .reg .b64 %rd<5>;
+; CHECK-EMPTY:
+; CHECK: ld.param.u64 %rd1, [foo_param_0];
+; CHECK: ld.param.u64 %rd2, [foo_param_1];
+; CHECK: cvta.to.global.u64 %rd3, %rd2;
+; CHECK: cvta.to.global.u64 %rd4, %rd1;
+; CHECK: ld.global.nc.u8 %rs1, [%rd4];
+; CHECK: cvt.u32.u8 %r1, %rs1;
+; CHECK: add.s32 %r2, %r1, 1;
+; CHECK: and.b32 %r3, %r2, 1;
+; CHECK: st.global.u32 [%rd3], %r3;
+; CHECK: ret;
+ %ld = load i1, ptr %ptr, align 1
+ %zext = zext i1 %ld to i32
+ %add = add i32 %zext, 1
+ %and = and i32 %add, 1
+ store i32 %and, ptr %retval
+ ret void
+}
+
+!nvvm.annotations = !{!0}
+
+!0 = !{ptr @foo, !"kernel", i32 1}
diff --git a/llvm/test/CodeGen/NVPTX/i1-load-lower.ll b/llvm/test/CodeGen/NVPTX/i1-load-lower.ll
new file mode 100644
index 0000000000000..d1f99b5724de8
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/i1-load-lower.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --function foo --extra_scrub --default-march nvptx64 --filter-out ".*//.*" --filter-out "[\(\)\{\}]" --version 5
+
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
+
+target triple = "nvptx-nvidia-cuda"
+
+@i1g = addrspace(1) global i1 false, align 2
+
+define void @foo() {
+; CHECK-LABEL: foo(
+; CHECK: .reg .pred %p<2>;
+; CHECK: .reg .b16 %rs<4>;
+; CHECK-EMPTY:
+; CHECK: ld.global.u8 %rs1, [i1g];
+; CHECK: and.b16 %rs2, %rs1, 1;
+; CHECK: setp.eq.b16 %p1, %rs2, 1;
+; CHECK: @%p1 bra $L__BB0_2;
+; CHECK: mov.u16 %rs3, 1;
+; CHECK: st.global.u8 [i1g], %rs3;
+; CHECK: ret;
+ %tmp = load i1, ptr addrspace(1) @i1g, align 2
+ br i1 %tmp, label %if.end, label %if.then
+
+if.then:
+ store i1 true, ptr addrspace(1) @i1g, align 2
+ br label %if.end
+
+if.end:
+ ret void
+}
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Thanks @Artem-B! I do not have write permissions yet- could you please merge for me? |
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Will do once the pending checks pass. |
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Thanks! Please use my author details: Meredith Julian [email protected] when you do merge. |
It will be whatever you used in your git commit. I just mash the button on github. The final commit will be "Authored by , Committed by ". I'll merge it tomorrow. Let me know if you want me to hold it for longer, if you need more time to update the pull request. |
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Ah perfect, that's what I used to commit. It should be good to go whenever pipelines pass. Thanks! |
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Looks like it is good to merge. Let me know if anything else is needed. |
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@mjulian31 Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested Please check whether problems have been caused by your change specifically, as How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
Summary: Currently, an illegal 2-byte load from a 1-byte global variable is being generated. This change instead generates a 1-byte load and zero-extends it to i16 register. This was always the intended behavior of the function. In addition, an i1 ext load of any kind needs to be promoted. A missing setLoadExtAction for ISD::EXTLOAD was causing an "Unhandled source type" unreachable due to an illegal i1 ext load during ISelDAGtoDAG (see below bug). Bug #98033. Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251000
Currently, an illegal 2-byte load from a 1-byte global variable is being generated. This change instead generates a 1-byte load and zero-extends it to i16 register. This was always the intended behavior of the function.
In addition, an i1 ext load of any kind needs to be promoted. A missing setLoadExtAction for ISD::EXTLOAD was causing an "Unhandled source type" unreachable due to an illegal i1 ext load during ISelDAGtoDAG (see below bug).
Bug #98033.