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[GISel][RISCV] Anyextend before copying f16 -> i32/i64 #94993

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Merged
merged 3 commits into from
Jun 10, 2024
Merged

[GISel][RISCV] Anyextend before copying f16 -> i32/i64 #94993

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67373a6
[GISel][RISCV] Anyextend before copying f16 -> i32/i64
dtcxzyw Jun 10, 2024
4b6d1eb
[GISel][RISCV] Format code. NFC.
dtcxzyw Jun 10, 2024
4d476f7
[GISel][RISCV] Address review comments. NFC.
dtcxzyw Jun 10, 2024
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11 changes: 8 additions & 3 deletions llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -102,9 +102,14 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {

void assignValueToReg(Register ValVReg, Register PhysReg,
const CCValAssign &VA) override {
// If we're passing an f32 value into an i64, anyextend before copying.
if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32)
ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(64), ValVReg).getReg(0);
// If we're passing a smaller fp value into a larger integer register,
// anyextend before copying.
if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||
((VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::i64) &&
VA.getValVT() == MVT::f16)) {
LLT DstTy = LLT::scalar(VA.getLocVT().getSizeInBits());
ValVReg = MIRBuilder.buildAnyExt(DstTy, ValVReg).getReg(0);
}

Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
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