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[AArch64] Disable red-zone when lowering Q-reg copy through memory. #94962

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Merged
merged 2 commits into from
Jun 11, 2024
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[AArch64] Disable red-zone when lowering Q-reg copy through memory. #94962

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8e2a8c2
[AArch64] Disable red-zone when lowering Q-reg copy through memory.
sdesmalen-arm Jun 10, 2024
d4f576a
Add hasFPARMv8 to avoid impact on soft-fp code
sdesmalen-arm Jun 10, 2024
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10 changes: 9 additions & 1 deletion llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -431,8 +431,16 @@ bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
uint64_t NumBytes = AFI->getLocalStackSize();

// If neither NEON or SVE are available, a COPY from one Q-reg to
// another requires a spill -> reload sequence. We can do that
// using a pre-decrementing store/post-decrementing load, but
// if we do so, we can't use the Red Zone.
bool LowerQRegCopyThroughMem = Subtarget.hasFPARMv8() &&
!Subtarget.isNeonAvailable() &&
!Subtarget.hasSVE();

return !(MFI.hasCalls() || hasFP(MF) || NumBytes > RedZoneSize ||
getSVEStackSize(MF));
getSVEStackSize(MF) || LowerQRegCopyThroughMem);
}

/// hasFP - Return true if the specified function should have a dedicated frame
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13 changes: 13 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-redzone.ll
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Expand Up @@ -16,3 +16,16 @@ define i32 @foo(i32 %a, i32 %b) nounwind ssp {
%tmp2 = load i32, ptr %x, align 4
ret i32 %tmp2
}

; We disable red-zone if NEON is available because copies of Q-regs
; require a spill/fill and dynamic allocation. But we only need to do
; this when FP registers are enabled.
define void @bar(fp128 %f) "target-features"="-fp-armv8" {
; CHECK-LABEL: bar:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x0, x1, [sp, #-16]
; CHECK-NEXT: ret
%ptr = alloca fp128
store fp128 %f, ptr %ptr
ret void
}
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