[RISCV] Support Zama16b1p0 #88474

jaidTw · 2024-04-12T06:10:02Z

This patch adds the support for Zama16b version 1.0, which has been added to RVA23U64 optional extensions recently
Ref: rva23-profile

This patch adds the support for Zama16b, which has been added to RVA23U64 optional extensions recently

github-actions · 2024-04-12T06:10:27Z

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be
notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write
permissions for the repository. In which case you can instead tag reviewers by
name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review
by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate
is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

llvmbot · 2024-04-12T06:11:01Z

@llvm/pr-subscribers-llvm-support
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: Jesse Huang (jaidTw)

Changes

This patch adds the support for Zama16b version 1.0, which has been added to RVA23U64 optional extensions recently
Ref: rva23-profile

Full diff: https://github.com/llvm/llvm-project/pull/88474.diff

6 Files Affected:

(modified) clang/test/Preprocessor/riscv-target-features.c (+7)
(modified) llvm/lib/Support/RISCVISAInfo.cpp (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+7)
(modified) llvm/test/CodeGen/RISCV/attributes.ll (+4)
(modified) llvm/test/MC/RISCV/attribute-arch.s (+3)
(modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+1)

diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index ec7764bb538189..21ad0b4e3d762c 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -79,6 +79,7 @@
 // CHECK-NOT: __riscv_za128rs {{.*$}}
 // CHECK-NOT: __riscv_za64rs {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
+// CHECK-NOT: __riscv_zama16b {{.*$}}
 // CHECK-NOT: __riscv_zawrs {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -704,6 +705,12 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
 // CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
 
+// RUN: %clang --target=riscv32 -march=rv32izama16b -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAMA16B-EXT %s
+// RUN: %clang --target=riscv64 -march=rv64izama16b  -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAMA16B-EXT %s
+// CHECK-ZAMA16B-EXT: __riscv_zama16b  1000000{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32izawrs -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZAWRS-EXT %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a19d24d1ff483..e047da1f9eeb3c 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -119,6 +119,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
     {"za128rs", {1, 0}},
     {"za64rs", {1, 0}},
     {"zacas", {1, 0}},
+    {"zama16b", {1, 0}},
     {"zawrs", {1, 0}},
 
     {"zba", {1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 794455aa730400..84d3176deeb952 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -208,6 +208,13 @@ def HasStdExtAOrZalrsc
                          "'A' (Atomic Instructions) or "
                          "'Zalrsc' (Load-Reserved/Store-Conditional)">;
 
+def FeatureStdExtZama16b
+    : SubtargetFeature<"zama16b", "HasStdExtZama16b", "true",
+                       "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
+def HasStdExtZama16b : Predicate<"Subtarget->hasStdExtZama16b()">,
+                       AssemblerPredicate<(all_of FeatureStdExtZama16b),
+                           "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
+
 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
                                           "'Zawrs' (Wait on Reservation Set)">;
 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 2326599bf35136..080783fdeec024 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -115,6 +115,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
+; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnpm  %s -o - | FileCheck --check-prefix=RV32SSNPM %s
@@ -199,6 +200,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAMA16B %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
@@ -370,6 +372,7 @@
 ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
 ; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
 ; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p2"
+; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
 ; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
 ; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0"
 ; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm0p8"
@@ -418,6 +421,7 @@
 ; RV64ZICBOZ: .attribute 5, "rv64i2p1_zicboz1p0"
 ; RV64ZA64RS: .attribute 5, "rv64i2p1_za64rs1p0"
 ; RV64ZA128RS: .attribute 5, "rv64i2p1_za128rs1p0"
+; RV64ZAMA16B: .attribute 5, "rv64i2p1_zama16b1p0"
 ; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0"
 ; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0"
 ; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index a8f493f781ec3d..8835ff22446c8d 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -270,6 +270,9 @@
 .attribute arch, "rv32iza64rs1p0"
 # CHECK: attribute      5, "rv32i2p1_za64rs1p0"
 
+.attribute arch, "rv32izama16b"
+# CHECK: attribute      5, "rv32i2p1_zama16b1p0"
+
 .attribute arch, "rv32izawrs1p0"
 # CHECK: attribute      5, "rv32i2p1_zawrs1p0"
 
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 67012d2e6dc720..caf7bf0a317174 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -769,6 +769,7 @@ R"(All available -march extensions for RISC-V
     za128rs              1.0
     za64rs               1.0
     zacas                1.0
+    zama16b              1.0
     zawrs                1.0
     zfa                  1.0
     zfh                  1.0

clang/test/Preprocessor/riscv-target-features.c

topperc

LGTM

kito-cheng · 2024-04-17T00:16:30Z

llvm/docs/RISCVUsage.rst need update

topperc

Need to update RISCVUsage.rst

llvm/docs/RISCVUsage.rst

kito-cheng

LGTM

wangpc-pp · 2024-04-17T04:27:52Z

Can you add it to RVA23 profile?

llvm-project/llvm/lib/Support/RISCVISAInfo.cpp

Lines 250 to 284 in f71e25b

    
           static constexpr RISCVProfile SupportedProfiles[] = { 
        
               {"rvi20u32", "rv32i"}, 
        
               {"rvi20u64", "rv64i"}, 
        
               {"rva20u64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"}, 
        
               {"rva20s64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_" 
        
                            "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"}, 
        
               {"rva22u64", 
        
                "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" 
        
                "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"}, 
        
               {"rva22s64", 
        
                "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" 
        
                "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_ssccptr_" 
        
                "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"}, 
        
               {"rva23u64", 
        
                "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" 
        
                "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_" 
        
                "zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"}, 
        
               {"rva23s64", 
        
                "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" 
        
                "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" 
        
                "zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_" 
        
                "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_" 
        
                "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_" 
        
                "svbare_svinval_svnapot_svpbmt"}, 
        
               {"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_" 
        
                            "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_" 
        
                            "zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"}, 
        
               {"rvb23s64", 
        
                "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" 
        
                "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" 
        
                "zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_" 
        
                "sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"}, 
        
               {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_" 
        
                            "zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"}, 
        
           };

topperc · 2024-04-17T04:28:49Z

Can you add it to RVA23 profile?

llvm-project/llvm/lib/Support/RISCVISAInfo.cpp

Lines 250 to 284 in f71e25b

static constexpr RISCVProfile SupportedProfiles[] = {

{"rvi20u32", "rv32i"},

{"rvi20u64", "rv64i"},

{"rva20u64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},

{"rva20s64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"

"za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},

{"rva22u64",

"rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},

{"rva22s64",

"rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_ssccptr_"

"sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},

{"rva23u64",

"rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_"

"zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},

{"rva23s64",

"rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"

"zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_"

"shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"

"sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"

"svbare_svinval_svnapot_svpbmt"},

{"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"

"zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"

"zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"},

{"rvb23s64",

"rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"

"zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_"

"sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},

{"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_"

"zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"},

};

It's an optional extension so I don't think it should be in the RVA23 profile.

wangpc-pp · 2024-04-17T04:28:50Z

Can you add it to RVA23 profile?

llvm-project/llvm/lib/Support/RISCVISAInfo.cpp

Lines 250 to 284 in f71e25b

static constexpr RISCVProfile SupportedProfiles[] = {

{"rvi20u32", "rv32i"},

{"rvi20u64", "rv64i"},

{"rva20u64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},

{"rva20s64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"

"za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},

{"rva22u64",

"rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},

{"rva22s64",

"rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_ssccptr_"

"sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},

{"rva23u64",

"rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_"

"zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},

{"rva23s64",

"rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"

"zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_"

"shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"

"sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"

"svbare_svinval_svnapot_svpbmt"},

{"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"

"zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"

"zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"},

{"rvb23s64",

"rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"

"zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"

"zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_"

"sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},

{"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_"

"zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"},

};

Never mind, it's an optional extension.

wangpc-pp

LGTM.

topperc

LGTM

github-actions · 2024-04-17T06:36:48Z

@jaidTw Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested
by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

Please check whether problems have been caused by your change specifically, as
the builds can include changes from many authors. It is not uncommon for your
change to be included in a build that fails due to someone else's changes, or
infrastructure issues.

How to do this, and the rest of the post-merge process, is covered in detail here.

If your change does cause a problem, it may be reverted, or you can revert it yourself.
This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again.

If you don't get any reports, no action is required from you. Your changes are working as expected, well done!

This reverts commit b090569.

[RISCV] Support Zama16b1p0

59b5216

This patch adds the support for Zama16b, which has been added to RVA23U64 optional extensions recently

jaidTw requested a review from topperc April 12, 2024 06:10

llvmbot added clang Clang issues not falling into any other category backend:RISC-V mc Machine (object) code llvm:support labels Apr 12, 2024

wangpc-pp reviewed Apr 12, 2024

View reviewed changes

clang/test/Preprocessor/riscv-target-features.c Outdated Show resolved Hide resolved

fixup indentation

b98b36e

topperc approved these changes Apr 17, 2024

View reviewed changes

topperc requested a review from wangpc-pp April 17, 2024 00:34

topperc requested changes Apr 17, 2024

View reviewed changes

UpdateRISCVUsage.rst

aafd461

kito-cheng reviewed Apr 17, 2024

View reviewed changes

llvm/docs/RISCVUsage.rst Outdated Show resolved Hide resolved

jaidTw requested a review from topperc April 17, 2024 01:53

Add description to profile note

f61763b

kito-cheng approved these changes Apr 17, 2024

View reviewed changes

wangpc-pp approved these changes Apr 17, 2024

View reviewed changes

topperc approved these changes Apr 17, 2024

View reviewed changes

jaidTw merged commit b090569 into llvm:main Apr 17, 2024

jaidTw deleted the zama16b branch April 17, 2024 06:36

ZijunZhaoCCK added a commit that referenced this pull request Apr 17, 2024

Revert "[RISCV] Support Zama16b1p0 (#88474)"

5f2c198

This reverts commit b090569.

ZijunZhaoCCK mentioned this pull request Apr 17, 2024

Revert "[RISCV] Support Zama16b1p0" #89122

Closed

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[RISCV] Support Zama16b1p0 #88474

[RISCV] Support Zama16b1p0 #88474

Uh oh!

jaidTw commented Apr 12, 2024

Uh oh!

github-actions bot commented Apr 12, 2024

Uh oh!

llvmbot commented Apr 12, 2024 •

edited

Loading

Uh oh!

Uh oh!

topperc left a comment

Uh oh!

kito-cheng commented Apr 17, 2024

Uh oh!

topperc left a comment

Uh oh!

Uh oh!

kito-cheng left a comment

Uh oh!

wangpc-pp commented Apr 17, 2024

Uh oh!

topperc commented Apr 17, 2024

Uh oh!

wangpc-pp commented Apr 17, 2024

Uh oh!

wangpc-pp left a comment

Uh oh!

topperc left a comment

Uh oh!

github-actions bot commented Apr 17, 2024

Uh oh!

Uh oh!

[RISCV] Support Zama16b1p0 #88474

[RISCV] Support Zama16b1p0 #88474

Uh oh!

Conversation

jaidTw commented Apr 12, 2024

Uh oh!

github-actions bot commented Apr 12, 2024

Uh oh!

llvmbot commented Apr 12, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Uh oh!

topperc left a comment

Choose a reason for hiding this comment

Uh oh!

kito-cheng commented Apr 17, 2024

Uh oh!

topperc left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

kito-cheng left a comment

Choose a reason for hiding this comment

Uh oh!

wangpc-pp commented Apr 17, 2024

Uh oh!

topperc commented Apr 17, 2024

Uh oh!

wangpc-pp commented Apr 17, 2024

Uh oh!

wangpc-pp left a comment

Choose a reason for hiding this comment

Uh oh!

topperc left a comment

Choose a reason for hiding this comment

Uh oh!

github-actions bot commented Apr 17, 2024

Uh oh!

Uh oh!

llvmbot commented Apr 12, 2024 •

edited

Loading