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[RISCV] Reverse (add x, (zext c)) back to (select c, (add x, 1), x) #87236

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[RISCV] Reverse (add x, (zext c)) back to (select c, (add x, 1), x) #87236

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fb91c9d
Add tests for converting i1 zext into select in RISCVCodeGenPrepare
lukel97 Apr 1, 2024
8dd319b
[RISCV] Reverse (add x, (zext c)) back to (select c, (add x, 1), x)
lukel97 Apr 1, 2024
994521c
Generalize from add to bin op (whoops)
lukel97 Apr 1, 2024
54880bd
Copy IR flags
lukel97 Apr 1, 2024
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48 changes: 48 additions & 0 deletions llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
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Expand Up @@ -52,12 +52,60 @@ class RISCVCodeGenPrepare : public FunctionPass,
}

bool visitInstruction(Instruction &I) { return false; }
bool visitBinaryOperator(BinaryOperator &BO);
bool visitAnd(BinaryOperator &BO);
bool visitIntrinsicInst(IntrinsicInst &I);
};

} // end anonymous namespace

/// InstCombine will canonicalize selects of binary ops where the identity is
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Why does this need to be done on IR instead of SelectionDAG?

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Just seemed like the right place to put it since it's undoing an InstCombine transform. I don't think there should be any issue doing it as a DAG combine. Would that be preferred?

/// zero to zexts:
///
/// select c, (add x, 1), x -> add x, (zext c)
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Can we also handle select c, (sub x, 1), x -> add x, (sext c)?

///
/// On RISC-V though, a zext of an i1 vector will be lowered as a vmv.v.i and a
/// vmerge.vim:
///
/// vmv.v.i v12, 0
/// vmerge.vim v9, v12, 1, v0
/// vadd.vv v8, v8, v9
///
/// Reverse this transform so that we pull the select outside of the binary op,
/// which allows us to fold it into a masked op:
///
/// vadd.vi v8, v8, 1, v0.t
bool RISCVCodeGenPrepare::visitBinaryOperator(BinaryOperator &BO) {
if (!BO.getType()->isVectorTy())
return false;

// TODO: We could allow sub if we did a non-commutative match
Constant *Identity = ConstantExpr::getIdentity(&BO, BO.getType());
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I've left the sub case for later, since I believe InstCombine canonicalizes sub x, (zext c) to add x, (sext c) anyway. Definitely something that the loop vectorizer could be emitting though

if (!Identity || !Identity->isNullValue())
return false;

using namespace PatternMatch;

Value *Mask, *RHS;
if (!match(&BO, m_c_BinOp(m_OneUse(m_ZExt(m_Value(Mask))), m_Value(RHS))))
return false;

if (!Mask->getType()->isIntOrIntVectorTy(1))
return false;

IRBuilder<> Builder(&BO);
Value *Splat = ConstantInt::get(BO.getType(), 1);
Value *NewBO = Builder.CreateBinOp(BO.getOpcode(), RHS, Splat);
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This requires a freeze on RHS

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I think I'm missing something here. We aren't increasing the number of uses of RHS and alive doesn't seem to complain. And we're not speculatively executing anything?

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Isn't RHS used by NewBO and Select?

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Sorry yes, I missed that.

I'm guessing the reason why alive doesn't require the freeze then is because (add (zext c), undef) ~> undef. So select c, (add undef, 1), undef would also be just as undefined?

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Freeze is unnecessary here because we only use one arm of the select inst.

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Why does foldBinOpIntoSelect use a freeze then?

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Why does foldBinOpIntoSelect use a freeze then?

https://github.com/llvm/llvm-project/blob/8bb9443333e0117ab61feecce9de339b11b924fc/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L2375-L2388

IIUC the freeze can be eliminated as well.

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Related patch: https://reviews.llvm.org/D118644

if (Instruction *I = dyn_cast<Instruction>(NewBO))
I->copyIRFlags(&BO);
Value *Select = Builder.CreateSelect(Mask, NewBO, RHS);

BO.replaceAllUsesWith(Select);
BO.eraseFromParent();

return true;
}

// Try to optimize (i64 (and (zext/sext (i32 X), C1))) if C1 has bit 31 set,
// but bits 63:32 are zero. If we know that bit 31 of X is 0, we can fill
// the upper 32 bits with ones.
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28 changes: 16 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
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Expand Up @@ -168,13 +168,14 @@ define <8 x i64> @vaaddu_vv_v8i64_floor(<8 x i64> %x, <8 x i64> %y) {
define <8 x i1> @vaaddu_vv_v8i1_floor(<8 x i1> %x, <8 x i1> %y) {
; CHECK-LABEL: vaaddu_vv_v8i1_floor:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vmv1r.v v9, v0
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Is this an improvement?

; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: csrwi vxrm, 2
; CHECK-NEXT: vaaddu.vv v8, v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 1
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
Expand Down Expand Up @@ -421,13 +422,16 @@ define <8 x i64> @vaaddu_vv_v8i64_ceil(<8 x i64> %x, <8 x i64> %y) {
define <8 x i1> @vaaddu_vv_v8i1_ceil(<8 x i1> %x, <8 x i1> %y) {
; CHECK-LABEL: vaaddu_vv_v8i1_ceil:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: csrwi vxrm, 0
; CHECK-NEXT: vaaddu.vv v8, v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: csrwi vxrm, 2
; CHECK-NEXT: vaaddu.vx v8, v8, a0
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
Expand Down
61 changes: 61 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
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Expand Up @@ -42,3 +42,64 @@ vector.body:
exit:
ret float %acc
}

define <vscale x 2 x i32> @i1_zext_add(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: i1_zext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: ret
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%add = add <vscale x 2 x i32> %b, %zext
ret <vscale x 2 x i32> %add
}

define <vscale x 2 x i32> @i1_zext_add_commuted(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: i1_zext_add_commuted:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: ret
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%add = add <vscale x 2 x i32> %zext, %b
ret <vscale x 2 x i32> %add
}

define <vscale x 2 x i32> @i1_zext_add_multi_use(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, ptr %p) {
; CHECK-LABEL: i1_zext_add_multi_use:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vs1r.v v9, (a0)
; CHECK-NEXT: ret
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%add = add <vscale x 2 x i32> %b, %zext
store <vscale x 2 x i32> %zext, ptr %p
ret <vscale x 2 x i32> %add
}

define <vscale x 2 x i32> @i1_zext_sub(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: i1_zext_sub:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: ret
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%sub = sub <vscale x 2 x i32> %b, %zext
ret <vscale x 2 x i32> %sub
}

define <vscale x 2 x i32> @i1_zext_or(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: i1_zext_or:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vor.vi v8, v8, 1, v0.t
; CHECK-NEXT: ret
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%or = or <vscale x 2 x i32> %b, %zext
ret <vscale x 2 x i32> %or
}
78 changes: 78 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
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Expand Up @@ -44,3 +44,81 @@ vector.body:
exit:
ret float %acc
}

define <vscale x 2 x i32> @i1_zext_add(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: define <vscale x 2 x i32> @i1_zext_add(
; CHECK-SAME: <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i32> [[B:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[ZEXT:%.*]] = zext <vscale x 2 x i1> [[A]] to <vscale x 2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = add <vscale x 2 x i32> [[B]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i64 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 2 x i1> [[A]], <vscale x 2 x i32> [[TMP1]], <vscale x 2 x i32> [[B]]
; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP2]]
;
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%add = add <vscale x 2 x i32> %b, %zext
ret <vscale x 2 x i32> %add
}

define <vscale x 2 x i32> @i1_zext_add_commuted(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: define <vscale x 2 x i32> @i1_zext_add_commuted(
; CHECK-SAME: <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i32> [[B:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[ZEXT:%.*]] = zext <vscale x 2 x i1> [[A]] to <vscale x 2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = add <vscale x 2 x i32> [[B]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i64 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 2 x i1> [[A]], <vscale x 2 x i32> [[TMP1]], <vscale x 2 x i32> [[B]]
; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP2]]
;
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%add = add <vscale x 2 x i32> %zext, %b
ret <vscale x 2 x i32> %add
}

define <vscale x 2 x i32> @i1_zext_add_multi_use(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, ptr %p) {
; CHECK-LABEL: define <vscale x 2 x i32> @i1_zext_add_multi_use(
; CHECK-SAME: <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i32> [[B:%.*]], ptr [[P:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[ZEXT:%.*]] = zext <vscale x 2 x i1> [[A]] to <vscale x 2 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = add <vscale x 2 x i32> [[B]], [[ZEXT]]
; CHECK-NEXT: store <vscale x 2 x i32> [[ZEXT]], ptr [[P]], align 8
; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP2]]
;
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%add = add <vscale x 2 x i32> %b, %zext
store <vscale x 2 x i32> %zext, ptr %p
ret <vscale x 2 x i32> %add
}

define <vscale x 2 x i32> @i1_zext_add_flags(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: define <vscale x 2 x i32> @i1_zext_add_flags(
; CHECK-SAME: <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i32> [[B:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[ZEXT:%.*]] = zext <vscale x 2 x i1> [[A]] to <vscale x 2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw <vscale x 2 x i32> [[B]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i64 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 2 x i1> [[A]], <vscale x 2 x i32> [[TMP1]], <vscale x 2 x i32> [[B]]
; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP2]]
;
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%add = add nuw nsw <vscale x 2 x i32> %b, %zext
ret <vscale x 2 x i32> %add
}

define <vscale x 2 x i32> @i1_zext_sub(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: define <vscale x 2 x i32> @i1_zext_sub(
; CHECK-SAME: <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i32> [[B:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[ZEXT:%.*]] = zext <vscale x 2 x i1> [[A]] to <vscale x 2 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = sub <vscale x 2 x i32> [[B]], [[ZEXT]]
; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP2]]
;
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%sub = sub <vscale x 2 x i32> %b, %zext
ret <vscale x 2 x i32> %sub
}

define <vscale x 2 x i32> @i1_zext_or(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: define <vscale x 2 x i32> @i1_zext_or(
; CHECK-SAME: <vscale x 2 x i1> [[A:%.*]], <vscale x 2 x i32> [[B:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[ZEXT:%.*]] = zext <vscale x 2 x i1> [[A]] to <vscale x 2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = or <vscale x 2 x i32> [[B]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i64 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 2 x i1> [[A]], <vscale x 2 x i32> [[TMP1]], <vscale x 2 x i32> [[B]]
; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP2]]
;
%zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32>
%or = or <vscale x 2 x i32> %b, %zext
ret <vscale x 2 x i32> %or
}
27 changes: 10 additions & 17 deletions llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
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Expand Up @@ -1365,23 +1365,13 @@ define <vscale x 8 x i64> @vwaddu_wx_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, i8 %
; Make sure that we don't introduce any V{S,Z}EXT_VL nodes with i1 types from
; combineBinOp_VLToVWBinOp_VL, since they can't be selected.
define <vscale x 1 x i64> @i1_zext(<vscale x 1 x i1> %va, <vscale x 1 x i64> %vb, ptr %p) {
; RV32-LABEL: i1_zext:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vadd.vv v8, v9, v8
; RV32-NEXT: li a1, 42
; RV32-NEXT: sh a1, 0(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: i1_zext:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; RV64-NEXT: vadd.vi v8, v8, 1, v0.t
; RV64-NEXT: li a1, 42
; RV64-NEXT: sh a1, 0(a0)
; RV64-NEXT: ret
; CHECK-LABEL: i1_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: li a1, 42
; CHECK-NEXT: sh a1, 0(a0)
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i1> %va to <vscale x 1 x i64>
%vd = add <vscale x 1 x i64> %vc, %vb

Expand Down Expand Up @@ -1466,3 +1456,6 @@ define <vscale x 2 x i32> @vwadd_wv_disjoint_or(<vscale x 2 x i32> %x.i32, <vsca
%or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32
ret <vscale x 2 x i32> %or
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}