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[X86][MC] Fix wrong encoding of promoted BMI instructions due to missing NoCD8 #78386

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Jan 18, 2024
Merged

[X86][MC] Fix wrong encoding of promoted BMI instructions due to missing NoCD8 #78386

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9bc8ee2
[X86][MC] Fix wrong encoding due to missing NoCD8
XinWang10 Jan 17, 2024
199c97b
rewrite bmi_pdep_pext
XinWang10 Jan 17, 2024
4b5432b
remove redundant argu
XinWang10 Jan 17, 2024
db6b576
remove ld_frag
XinWang10 Jan 18, 2024
ecf8857
extract T8 to class
XinWang10 Jan 18, 2024
db62833
rename
XinWang10 Jan 18, 2024
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45 changes: 18 additions & 27 deletions llvm/lib/Target/X86/X86InstrMisc.td
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Expand Up @@ -1375,39 +1375,30 @@ let Predicates = [HasBMI2, NoTBM, HasEGPR] in {
(MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
}

multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
X86MemOperand x86memop, SDPatternOperator OpNode,
PatFrag ld_frag, string Suffix = ""> {
def rr#Suffix : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>,
NoCD8, VVVV, Sched<[WriteALU]>;
def rm#Suffix : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>,
NoCD8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
multiclass PdepPext<string m, X86TypeInfo t, SDPatternOperator node,
string suffix = ""> {
def rr#suffix : ITy<0xF5, MRMSrcReg, t, (outs t.RegClass:$dst),
(ins t.RegClass:$src1, t.RegClass:$src2), m, binop_ndd_args,
[(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2))]>,
T8, VVVV, Sched<[WriteALU]>;
def rm#suffix : ITy<0xF5, MRMSrcMem, t, (outs t.RegClass:$dst),
(ins t.RegClass:$src1, t.MemOperand:$src2), m, binop_ndd_args,
[(set t.RegClass:$dst, (node t.RegClass:$src1, (t.LoadNode addr:$src2)))]>,
T8, VVVV, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
}

let Predicates = [HasBMI2, NoEGPR] in {
defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
X86pdep, loadi32>, T8, XD, VEX;
defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
X86pdep, loadi64>, T8, XD, REX_W, VEX;
defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
X86pext, loadi32>, T8, XS, VEX;
defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
X86pext, loadi64>, T8, XS, REX_W, VEX;
defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep>, XD, VEX;
defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep>, XD, REX_W, VEX;
defm PEXT32 : PdepPext<"pext", Xi32, X86pext>, XS, VEX;
defm PEXT64 : PdepPext<"pext", Xi64, X86pext>, XS, REX_W, VEX;
}

let Predicates = [HasBMI2, HasEGPR] in {
defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
X86pdep, loadi32, "_EVEX">, T8, XD, EVEX;
defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
X86pdep, loadi64, "_EVEX">, T8, XD, REX_W, EVEX;
defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
X86pext, loadi32, "_EVEX">, T8, XS, EVEX;
defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
X86pext, loadi64, "_EVEX">, T8, XS, REX_W, EVEX;
defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep, "_EVEX">, XD, EVEX;
defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep, "_EVEX">, XD, REX_W, EVEX;
defm PEXT32 : PdepPext<"pext", Xi32, X86pext, "_EVEX">, XS, EVEX;
defm PEXT64 : PdepPext<"pext", Xi64, X86pext, "_EVEX">, XS, REX_W, EVEX;
}

//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrSSE.td
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Original file line number Diff line number Diff line change
Expand Up @@ -6663,14 +6663,14 @@ let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
class Crc32r<X86TypeInfo t, RegisterClass rc, SDPatternOperator node>
: ITy<0xF1, MRMSrcReg, t, (outs rc:$dst), (ins rc:$src1, t.RegClass:$src2),
"crc32", binop_args, [(set rc:$dst, (node rc:$src1, t.RegClass:$src2))]>,
Sched<[WriteCRC32]>, NoCD8 {
Sched<[WriteCRC32]> {
let Constraints = "$src1 = $dst";
}

class Crc32m<X86TypeInfo t, RegisterClass rc, SDPatternOperator node>
: ITy<0xF1, MRMSrcMem, t, (outs rc:$dst), (ins rc:$src1, t.MemOperand:$src2),
"crc32", binop_args, [(set rc:$dst, (node rc:$src1, (load addr:$src2)))]>,
Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]>, NoCD8 {
Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]> {
let Constraints = "$src1 = $dst";
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/X86/X86InstrUtils.td
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Original file line number Diff line number Diff line change
Expand Up @@ -113,9 +113,9 @@ class NDD<bit ndd, Map map = OB> {
Map OpMap = !if(!eq(ndd, 0), map, T_MAP4);
}
// NF - Helper for NF (no flags update) instructions
class NF: T_MAP4, EVEX, EVEX_NF, NoCD8;
class NF: T_MAP4, EVEX, EVEX_NF;
// PL - Helper for promoted legacy instructions
class PL: T_MAP4, EVEX, NoCD8, ExplicitEVEXPrefix;
class PL: T_MAP4, EVEX, ExplicitEVEXPrefix;

//===----------------------------------------------------------------------===//
// X86 Type infomation definitions
Expand Down Expand Up @@ -961,7 +961,7 @@ class ITy<bits<8> o, Format f, X86TypeInfo t, dag outs, dag ins, string m,
string args, list<dag> p>
: I<{o{7}, o{6}, o{5}, o{4}, o{3}, o{2}, o{1},
!if(!eq(t.HasEvenOpcode, 1), 0, o{0})}, f, outs, ins,
!strconcat(m, "{", t.InstrSuffix, "}\t", args), p> {
!strconcat(m, "{", t.InstrSuffix, "}\t", args), p>, NoCD8 {
let hasSideEffects = 0;
let hasREX_W = t.HasREX_W;
}
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/MC/Disassembler/X86/apx/bmi2.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -13,11 +13,11 @@

# ATT: mulxl 123(%rax,%rbx,4), %ecx, %edx
# INTEL: mulx edx, ecx, dword ptr [rax + 4*rbx + 123]
0x62,0xf2,0x77,0x08,0xf6,0x94,0x98,0x7b,0x00,0x00,0x00
0x62,0xf2,0x77,0x08,0xf6,0x54,0x98,0x7b

# ATT: mulxq 123(%rax,%rbx,4), %r9, %r15
# INTEL: mulx r15, r9, qword ptr [rax + 4*rbx + 123]
0x62,0x72,0xb7,0x08,0xf6,0xbc,0x98,0x7b,0x00,0x00,0x00
0x62,0x72,0xb7,0x08,0xf6,0x7c,0x98,0x7b

# ATT: mulxl %r18d, %r22d, %r26d
# INTEL: mulx r26d, r22d, r18d
Expand Down Expand Up @@ -115,11 +115,11 @@

# ATT: rorxl $123, 123(%rax,%rbx,4), %ecx
# INTEL: rorx ecx, dword ptr [rax + 4*rbx + 123], 123
0x62,0xf3,0x7f,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b
0x62,0xf3,0x7f,0x08,0xf0,0x4c,0x98,0x7b,0x7b

# ATT: rorxq $123, 123(%rax,%rbx,4), %r9
# INTEL: rorx r9, qword ptr [rax + 4*rbx + 123], 123
0x62,0x73,0xff,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b
0x62,0x73,0xff,0x08,0xf0,0x4c,0x98,0x7b,0x7b

# ATT: rorxl $123, %r18d, %r22d
# INTEL: rorx r22d, r18d, 123
Expand All @@ -145,15 +145,15 @@

# ATT: sarxl %ecx, 123(%rax,%rbx,4), %edx
# INTEL: sarx edx, dword ptr [rax + 4*rbx + 123], ecx
0x62,0xf2,0x76,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
0x62,0xf2,0x76,0x08,0xf7,0x54,0x98,0x7b

# ATT: sarxq %r9, %r15, %r11
# INTEL: sarx r11, r15, r9
0x62,0x52,0xb6,0x08,0xf7,0xdf

# ATT: sarxq %r9, 123(%rax,%rbx,4), %r15
# INTEL: sarx r15, qword ptr [rax + 4*rbx + 123], r9
0x62,0x72,0xb6,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
0x62,0x72,0xb6,0x08,0xf7,0x7c,0x98,0x7b

# ATT: sarxl %r18d, %r22d, %r26d
# INTEL: sarx r26d, r22d, r18d
Expand All @@ -179,15 +179,15 @@

# ATT: shlxl %ecx, 123(%rax,%rbx,4), %edx
# INTEL: shlx edx, dword ptr [rax + 4*rbx + 123], ecx
0x62,0xf2,0x75,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
0x62,0xf2,0x75,0x08,0xf7,0x54,0x98,0x7b

# ATT: shlxq %r9, %r15, %r11
# INTEL: shlx r11, r15, r9
0x62,0x52,0xb5,0x08,0xf7,0xdf

# ATT: shlxq %r9, 123(%rax,%rbx,4), %r15
# INTEL: shlx r15, qword ptr [rax + 4*rbx + 123], r9
0x62,0x72,0xb5,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
0x62,0x72,0xb5,0x08,0xf7,0x7c,0x98,0x7b

# ATT: shlxl %r18d, %r22d, %r26d
# INTEL: shlx r26d, r22d, r18d
Expand All @@ -213,15 +213,15 @@

# ATT: shrxl %ecx, 123(%rax,%rbx,4), %edx
# INTEL: shrx edx, dword ptr [rax + 4*rbx + 123], ecx
0x62,0xf2,0x77,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00
0x62,0xf2,0x77,0x08,0xf7,0x54,0x98,0x7b

# ATT: shrxq %r9, %r15, %r11
# INTEL: shrx r11, r15, r9
0x62,0x52,0xb7,0x08,0xf7,0xdf

# ATT: shrxq %r9, 123(%rax,%rbx,4), %r15
# INTEL: shrx r15, qword ptr [rax + 4*rbx + 123], r9
0x62,0x72,0xb7,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00
0x62,0x72,0xb7,0x08,0xf7,0x7c,0x98,0x7b

# ATT: shrxl %r18d, %r22d, %r26d
# INTEL: shrx r26d, r22d, r18d
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/MC/X86/apx/bmi2-att.s
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Original file line number Diff line number Diff line change
Expand Up @@ -15,11 +15,11 @@
{evex} mulxq %r9, %r15, %r11

# CHECK: {evex} mulxl 123(%rax,%rbx,4), %ecx, %edx
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x54,0x98,0x7b]
{evex} mulxl 123(%rax,%rbx,4), %ecx, %edx

# CHECK: {evex} mulxq 123(%rax,%rbx,4), %r9, %r15
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0x7c,0x98,0x7b]
{evex} mulxq 123(%rax,%rbx,4), %r9, %r15

# CHECK: mulxl %r18d, %r22d, %r26d
Expand Down Expand Up @@ -117,11 +117,11 @@
{evex} rorxq $123, %r9, %r15

# CHECK: {evex} rorxl $123, 123(%rax,%rbx,4), %ecx
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
{evex} rorxl $123, 123(%rax,%rbx,4), %ecx

# CHECK: {evex} rorxq $123, 123(%rax,%rbx,4), %r9
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
{evex} rorxq $123, 123(%rax,%rbx,4), %r9

# CHECK: rorxl $123, %r18d, %r22d
Expand All @@ -147,15 +147,15 @@
{evex} sarxl %ecx, %edx, %r10d

# CHECK: {evex} sarxl %ecx, 123(%rax,%rbx,4), %edx
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x54,0x98,0x7b]
{evex} sarxl %ecx, 123(%rax,%rbx,4), %edx

# CHECK: {evex} sarxq %r9, %r15, %r11
# CHECK: encoding: [0x62,0x52,0xb6,0x08,0xf7,0xdf]
{evex} sarxq %r9, %r15, %r11

# CHECK: {evex} sarxq %r9, 123(%rax,%rbx,4), %r15
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0x7c,0x98,0x7b]
{evex} sarxq %r9, 123(%rax,%rbx,4), %r15

# CHECK: sarxl %r18d, %r22d, %r26d
Expand All @@ -181,15 +181,15 @@
{evex} shlxl %ecx, %edx, %r10d

# CHECK: {evex} shlxl %ecx, 123(%rax,%rbx,4), %edx
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x54,0x98,0x7b]
{evex} shlxl %ecx, 123(%rax,%rbx,4), %edx

# CHECK: {evex} shlxq %r9, %r15, %r11
# CHECK: encoding: [0x62,0x52,0xb5,0x08,0xf7,0xdf]
{evex} shlxq %r9, %r15, %r11

# CHECK: {evex} shlxq %r9, 123(%rax,%rbx,4), %r15
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0x7c,0x98,0x7b]
{evex} shlxq %r9, 123(%rax,%rbx,4), %r15

# CHECK: shlxl %r18d, %r22d, %r26d
Expand All @@ -215,15 +215,15 @@
{evex} shrxl %ecx, %edx, %r10d

# CHECK: {evex} shrxl %ecx, 123(%rax,%rbx,4), %edx
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x54,0x98,0x7b]
{evex} shrxl %ecx, 123(%rax,%rbx,4), %edx

# CHECK: {evex} shrxq %r9, %r15, %r11
# CHECK: encoding: [0x62,0x52,0xb7,0x08,0xf7,0xdf]
{evex} shrxq %r9, %r15, %r11

# CHECK: {evex} shrxq %r9, 123(%rax,%rbx,4), %r15
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0x7c,0x98,0x7b]
{evex} shrxq %r9, 123(%rax,%rbx,4), %r15

# CHECK: shrxl %r18d, %r22d, %r26d
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/MC/X86/apx/bmi2-intel.s
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,11 @@
{evex} mulx r11, r15, r9

# CHECK: {evex} mulx edx, ecx, dword ptr [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf6,0x54,0x98,0x7b]
{evex} mulx edx, ecx, dword ptr [rax + 4*rbx + 123]

# CHECK: {evex} mulx r15, r9, qword ptr [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf6,0x7c,0x98,0x7b]
{evex} mulx r15, r9, qword ptr [rax + 4*rbx + 123]

# CHECK: mulx r26d, r22d, r18d
Expand Down Expand Up @@ -113,11 +113,11 @@
{evex} rorx r15, r9, 123

# CHECK: {evex} rorx ecx, dword ptr [rax + 4*rbx + 123], 123
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
# CHECK: encoding: [0x62,0xf3,0x7f,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
{evex} rorx ecx, dword ptr [rax + 4*rbx + 123], 123

# CHECK: {evex} rorx r9, qword ptr [rax + 4*rbx + 123], 123
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x8c,0x98,0x7b,0x00,0x00,0x00,0x7b]
# CHECK: encoding: [0x62,0x73,0xff,0x08,0xf0,0x4c,0x98,0x7b,0x7b]
{evex} rorx r9, qword ptr [rax + 4*rbx + 123], 123

# CHECK: rorx r22d, r18d, 123
Expand All @@ -143,15 +143,15 @@
{evex} sarx r10d, edx, ecx

# CHECK: {evex} sarx edx, dword ptr [rax + 4*rbx + 123], ecx
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x76,0x08,0xf7,0x54,0x98,0x7b]
{evex} sarx edx, dword ptr [rax + 4*rbx + 123], ecx

# CHECK: {evex} sarx r11, r15, r9
# CHECK: encoding: [0x62,0x52,0xb6,0x08,0xf7,0xdf]
{evex} sarx r11, r15, r9

# CHECK: {evex} sarx r15, qword ptr [rax + 4*rbx + 123], r9
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb6,0x08,0xf7,0x7c,0x98,0x7b]
{evex} sarx r15, qword ptr [rax + 4*rbx + 123], r9

# CHECK: sarx r26d, r22d, r18d
Expand All @@ -177,15 +177,15 @@
{evex} shlx r10d, edx, ecx

# CHECK: {evex} shlx edx, dword ptr [rax + 4*rbx + 123], ecx
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x75,0x08,0xf7,0x54,0x98,0x7b]
{evex} shlx edx, dword ptr [rax + 4*rbx + 123], ecx

# CHECK: {evex} shlx r11, r15, r9
# CHECK: encoding: [0x62,0x52,0xb5,0x08,0xf7,0xdf]
{evex} shlx r11, r15, r9

# CHECK: {evex} shlx r15, qword ptr [rax + 4*rbx + 123], r9
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb5,0x08,0xf7,0x7c,0x98,0x7b]
{evex} shlx r15, qword ptr [rax + 4*rbx + 123], r9

# CHECK: shlx r26d, r22d, r18d
Expand All @@ -211,15 +211,15 @@
{evex} shrx r10d, edx, ecx

# CHECK: {evex} shrx edx, dword ptr [rax + 4*rbx + 123], ecx
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0xf2,0x77,0x08,0xf7,0x54,0x98,0x7b]
{evex} shrx edx, dword ptr [rax + 4*rbx + 123], ecx

# CHECK: {evex} shrx r11, r15, r9
# CHECK: encoding: [0x62,0x52,0xb7,0x08,0xf7,0xdf]
{evex} shrx r11, r15, r9

# CHECK: {evex} shrx r15, qword ptr [rax + 4*rbx + 123], r9
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
# CHECK: encoding: [0x62,0x72,0xb7,0x08,0xf7,0x7c,0x98,0x7b]
{evex} shrx r15, qword ptr [rax + 4*rbx + 123], r9

# CHECK: shrx r26d, r22d, r18d
Expand Down