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[AMDGPU] Baseline gfx1250 speed model. #145217

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Merged
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Jun 23, 2025
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[AMDGPU] Baseline gfx1250 speed model. #145217

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/GCNProcessors.td
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Original file line number Diff line number Diff line change
Expand Up @@ -326,6 +326,6 @@ def : ProcessorModel<"gfx12-generic", GFX12SpeedModel,
FeatureISAVersion12_Generic.Features
>;

def : ProcessorModel<"gfx1250", GFX12SpeedModel,
def : ProcessorModel<"gfx1250", GFX1250SpeedModel,
FeatureISAVersion12_50.Features
>;
33 changes: 33 additions & 0 deletions llvm/lib/Target/AMDGPU/SISchedule.td
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Expand Up @@ -99,6 +99,7 @@ def SIDPGFX950FullSpeedModel : SISchedMachineModel;
def GFX10SpeedModel : SISchedMachineModel;
def GFX11SpeedModel : SISchedMachineModel;
def GFX12SpeedModel : SISchedMachineModel;
def GFX1250SpeedModel : SISchedMachineModel;

// XXX: Are the resource counts correct?
def HWBranch : ProcResource<1> {
Expand Down Expand Up @@ -455,3 +456,35 @@ def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;
def : InstRW<[WriteCopy], (instrs COPY)>;

} // End SchedModel = GFX12SpeedModel

multiclass GFX125xCommonWriteRes {

def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;
def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;
def : HWWriteRes<WriteTrans32, [HWTransVALU, HWRC], 7>;
def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 6>;
def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;
def : HWWriteRes<WritePseudoScalarTrans, [HWVALU, HWRC], 8>;
Comment on lines +464 to +467
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Why do WriteTrans32 and WritePseudoScalarTrans use different resources? And it seems unintuitive that the scalar trans cost is higher than trans32, is that correct?

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According to the spec it uses VALU pipeline. I suspect it uses both, but that is really what is written. Then it is of course inherited from the gfx12 baseline.

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And yes, it is correct it is higher, because you also need to move data to the pipeline.


def : HWWriteRes<WriteBranch, [HWBranch], 32>;
def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;
def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;
def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;
def : HWWriteRes<WriteSFPU, [HWSALU, HWRC], 4>;
def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;
def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;
def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;

def : InstRW<[WriteCopy], (instrs COPY)>;
} // End GFX125xCommonWriteRes

let SchedModel = GFX1250SpeedModel in {
defm : GFX125xCommonWriteRes;

def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 7>;
def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 11>;
def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 32>;
def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 32>;
def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 32>;
def : HWWriteRes<WriteTrans64, [HWVALU, HWTransVALU, HWRC], 38>;
} // SchedModel = GFX1250SpeedModel
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