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[RISCV] Allow larger offset when matching build_vector as vid sequence #144756

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Jun 20, 2025
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[RISCV] Allow larger offset when matching build_vector as vid sequence #144756

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3b91650
[RISCV] Allow larger offset when matching build_vector as vid sequence
preames Jun 18, 2025
5f08263
Update llvm/lib/Target/RISCV/RISCVISelLowering.cpp
preames Jun 19, 2025
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10 changes: 5 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -3724,14 +3724,14 @@ static SDValue lowerBuildVectorViaVID(SDValue Op, SelectionDAG &DAG,
SplatStepVal = Log2_64(std::abs(StepNumerator));
}

// Only emit VIDs with suitably-small steps/addends. We use imm5 is a
// threshold since it's the immediate value many RVV instructions accept.
// There is no vmul.vi instruction so ensure multiply constant can fit in
// a single addi instruction.
// Only emit VIDs with suitably-small steps. We use imm5 as a threshold
// since it's the immediate value many RVV instructions accept. There is
// no vmul.vi instruction so ensure multiply constant can fit in a
// single addi instruction. For the addend, we allow up to 32 bits..
if (((StepOpcode == ISD::MUL && isInt<12>(SplatStepVal)) ||
(StepOpcode == ISD::SHL && isUInt<5>(SplatStepVal))) &&
isPowerOf2_32(StepDenominator) &&
(SplatStepVal >= 0 || StepDenominator == 1) && isInt<5>(Addend)) {
(SplatStepVal >= 0 || StepDenominator == 1) && isInt<32>(Addend)) {
MVT VIDVT =
VT.isFloatingPoint() ? VT.changeVectorElementTypeToInteger() : VT;
MVT VIDContainerVT =
Expand Down
130 changes: 54 additions & 76 deletions llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
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Expand Up @@ -103,18 +103,16 @@ define <8 x i1> @fv8(ptr %p, i64 %index, i64 %tc) {
define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) {
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Not blocking for this patch but there's an extra ptr %p argument that isn't used.

; CHECK-LABEL: fv32:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v24, v16, a2
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v16
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: vslideup.vi v0, v24, 2
; CHECK-NEXT: ret
%mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc)
ret <32 x i1> %mask
Expand All @@ -125,30 +123,24 @@ define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_0)
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_1)
; CHECK-NEXT: vle8.v v17, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI9_2)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_2)
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vle8.v v18, (a0)
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v16
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vsaddu.vx v16, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v24, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v25, v16, a2
; CHECK-NEXT: li a0, 48
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v17
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v17, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: vslideup.vi v0, v24, 2
; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v0, v17, 4
; CHECK-NEXT: vslideup.vi v0, v25, 4
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf8 v8, v18
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v0, v16, 6
Expand All @@ -160,63 +152,49 @@ define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) {
define <128 x i1> @fv128(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv128:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_1)
; CHECK-NEXT: vle8.v v17, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_2)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_2)
; CHECK-NEXT: vle8.v v18, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_3)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_3)
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vle8.v v19, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_4)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_4)
; CHECK-NEXT: vle8.v v20, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_5)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_5)
; CHECK-NEXT: vle8.v v21, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI10_6)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_6)
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vle8.v v22, (a0)
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v16
; CHECK-NEXT: li a0, 80
; CHECK-NEXT: vsaddu.vx v16, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v24, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: li a0, 96
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v25, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: li a0, 112
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v26, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v27, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v28, v16, a2
; CHECK-NEXT: vadd.vx v16, v8, a0
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v29, v16, a2
; CHECK-NEXT: li a0, 48
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v17
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v17, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v18
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v18, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v19
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v19, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v20
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v20, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v21
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v21, v8, a2
; CHECK-NEXT: vsext.vf8 v8, v22
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v22, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v17, v16, 2
; CHECK-NEXT: vslideup.vi v0, v20, 2
; CHECK-NEXT: vslideup.vi v25, v24, 2
; CHECK-NEXT: vslideup.vi v0, v28, 2
; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v17, v18, 4
; CHECK-NEXT: vslideup.vi v0, v21, 4
; CHECK-NEXT: vslideup.vi v25, v26, 4
; CHECK-NEXT: vslideup.vi v0, v29, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v17, v19, 6
; CHECK-NEXT: vslideup.vi v0, v22, 6
; CHECK-NEXT: vslideup.vi v25, v27, 6
; CHECK-NEXT: vslideup.vi v0, v16, 6
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vslideup.vi v0, v17, 8
; CHECK-NEXT: vslideup.vi v0, v25, 8
; CHECK-NEXT: ret
%mask = call <128 x i1> @llvm.get.active.lane.mask.v128i1.i64(i64 %index, i64 %tc)
ret <128 x i1> %mask
Expand Down
16 changes: 10 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
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Expand Up @@ -94,21 +94,25 @@ define <2 x bfloat> @vid_v2bf16() {
define <2 x bfloat> @vid_addend1_v2bf16() {
; CHECK-LABEL: vid_addend1_v2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 262148
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: lui a0, 4
; CHECK-NEXT: vsll.vi v8, v8, 7
; CHECK-NEXT: addi a0, a0, -128
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: ret
ret <2 x bfloat> <bfloat 1.0, bfloat 2.0>
}

define <2 x bfloat> @vid_denominator2_v2bf16() {
; CHECK-LABEL: vid_denominator2_v2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 260100
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: lui a0, 4
; CHECK-NEXT: vsll.vi v8, v8, 7
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: ret
ret <2 x bfloat> <bfloat 0.5, bfloat 1.0>
}
Expand Down
40 changes: 24 additions & 16 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
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Expand Up @@ -1573,18 +1573,22 @@ define <2 x half> @vid_addend1_v2f16() {
;
; RV32ZVFHMIN-LABEL: vid_addend1_v2f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: lui a0, 262148
; RV32ZVFHMIN-NEXT: addi a0, a0, -1024
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32ZVFHMIN-NEXT: vid.v v8
; RV32ZVFHMIN-NEXT: li a0, 15
; RV32ZVFHMIN-NEXT: vsll.vi v8, v8, 10
; RV32ZVFHMIN-NEXT: slli a0, a0, 10
; RV32ZVFHMIN-NEXT: vadd.vx v8, v8, a0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vid_addend1_v2f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: lui a0, 262148
; RV64ZVFHMIN-NEXT: addi a0, a0, -1024
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64ZVFHMIN-NEXT: vid.v v8
; RV64ZVFHMIN-NEXT: li a0, 15
; RV64ZVFHMIN-NEXT: vsll.vi v8, v8, 10
; RV64ZVFHMIN-NEXT: slli a0, a0, 10
; RV64ZVFHMIN-NEXT: vadd.vx v8, v8, a0
; RV64ZVFHMIN-NEXT: ret
ret <2 x half> <half 1.0, half 2.0>
}
Expand All @@ -1608,18 +1612,22 @@ define <2 x half> @vid_denominator2_v2f16() {
;
; RV32ZVFHMIN-LABEL: vid_denominator2_v2f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: lui a0, 245764
; RV32ZVFHMIN-NEXT: addi a0, a0, -2048
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV32ZVFHMIN-NEXT: vid.v v8
; RV32ZVFHMIN-NEXT: li a0, 7
; RV32ZVFHMIN-NEXT: vsll.vi v8, v8, 10
; RV32ZVFHMIN-NEXT: slli a0, a0, 11
; RV32ZVFHMIN-NEXT: vadd.vx v8, v8, a0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vid_denominator2_v2f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: lui a0, 245764
; RV64ZVFHMIN-NEXT: addi a0, a0, -2048
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; RV64ZVFHMIN-NEXT: vid.v v8
; RV64ZVFHMIN-NEXT: li a0, 7
; RV64ZVFHMIN-NEXT: vsll.vi v8, v8, 10
; RV64ZVFHMIN-NEXT: slli a0, a0, 11
; RV64ZVFHMIN-NEXT: vadd.vx v8, v8, a0
; RV64ZVFHMIN-NEXT: ret
ret <2 x half> <half 0.5, half 1.0>
}
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
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Expand Up @@ -58,10 +58,10 @@ define void @buildvec_vid_plus_imm_v16i8(ptr %x) {
define void @buildvec_vid_plus_nonimm_v16i8(ptr %x) {
; CHECK-LABEL: buildvec_vid_plus_nonimm_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI4_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI4_0)
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: li a1, 100
; CHECK-NEXT: vadd.vx v8, v8, a1
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
store <16 x i8> <i8 100, i8 101, i8 102, i8 103, i8 104, i8 105, i8 106, i8 107, i8 108, i8 109, i8 110, i8 111, i8 112, i8 113, i8 114, i8 115>, ptr %x
Expand Down
30 changes: 12 additions & 18 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
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Expand Up @@ -1734,19 +1734,16 @@ define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m,
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: mv a2, a0
; RV32-NEXT: li a0, 32
; RV32-NEXT: lui a3, %hi(.LCPI72_0)
; RV32-NEXT: addi a3, a3, %lo(.LCPI72_0)
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vle8.v v12, (a3)
; RV32-NEXT: vid.v v16
; RV32-NEXT: vmsltu.vx v14, v16, a1
; RV32-NEXT: li a3, 64
; RV32-NEXT: vsext.vf4 v16, v12
; RV32-NEXT: vmsltu.vx v12, v16, a1
; RV32-NEXT: vadd.vx v16, v16, a0
; RV32-NEXT: vmsltu.vx v13, v16, a1
; RV32-NEXT: li a1, 64
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vi v14, v12, 4
; RV32-NEXT: vsetvli zero, a3, e8, m4, ta, ma
; RV32-NEXT: vmand.mm v0, v14, v0
; RV32-NEXT: vslideup.vi v12, v13, 4
; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; RV32-NEXT: vmand.mm v0, v12, v0
; RV32-NEXT: vmv.v.i v12, 1
; RV32-NEXT: vmerge.vvm v8, v12, v8, v0
; RV32-NEXT: vslidedown.vx v12, v8, a0
Expand Down Expand Up @@ -1780,19 +1777,16 @@ define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m,
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: mv a2, a0
; RV64-NEXT: li a0, 32
; RV64-NEXT: lui a3, %hi(.LCPI72_0)
; RV64-NEXT: addi a3, a3, %lo(.LCPI72_0)
; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV64-NEXT: vle8.v v12, (a3)
; RV64-NEXT: vid.v v16
; RV64-NEXT: vmsltu.vx v14, v16, a1
; RV64-NEXT: li a3, 64
; RV64-NEXT: vsext.vf4 v16, v12
; RV64-NEXT: vmsltu.vx v12, v16, a1
; RV64-NEXT: vadd.vx v16, v16, a0
; RV64-NEXT: vmsltu.vx v13, v16, a1
; RV64-NEXT: li a1, 64
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vi v14, v12, 4
; RV64-NEXT: vsetvli zero, a3, e8, m4, ta, ma
; RV64-NEXT: vmand.mm v0, v14, v0
; RV64-NEXT: vslideup.vi v12, v13, 4
; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; RV64-NEXT: vmand.mm v0, v12, v0
; RV64-NEXT: vmv.v.i v12, 1
; RV64-NEXT: vmerge.vvm v8, v12, v8, v0
; RV64-NEXT: vslidedown.vx v12, v8, a0
Expand Down
17 changes: 11 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
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Expand Up @@ -4,10 +4,12 @@
define void @foo_1(ptr nocapture noundef writeonly %t) {
; CHECK-LABEL: foo_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a1, %hi(.LCPI0_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI0_0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsll.vi v8, v8, 7
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: vadd.vx v8, v8, a1
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
entry:
Expand All @@ -18,10 +20,13 @@ entry:
define void @foo_2(ptr nocapture noundef writeonly %t) {
; CHECK-LABEL: foo_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a1, %hi(.LCPI1_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI1_0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: vsll.vi v8, v8, 7
; CHECK-NEXT: addi a1, a1, -512
; CHECK-NEXT: vadd.vx v8, v8, a1
; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
entry:
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