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ARM: Move ABI enum from TargetMachine to TargetParser #144725

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10 changes: 10 additions & 0 deletions llvm/include/llvm/TargetParser/ARMTargetParser.h
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,13 @@ class Triple;

namespace ARM {

enum ARMABI {
ARM_ABI_UNKNOWN,
ARM_ABI_APCS,
ARM_ABI_AAPCS, // ARM EABI
ARM_ABI_AAPCS16
};

// Arch extension modifiers for CPUs.
// Note that this is not the same as the AArch64 list
enum ArchExtKind : uint64_t {
Expand Down Expand Up @@ -265,6 +272,9 @@ LLVM_ABI unsigned parseArchVersion(StringRef Arch);
LLVM_ABI void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
LLVM_ABI StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);

LLVM_ABI ARMABI computeTargetABI(const Triple &TT, StringRef CPU,
StringRef ABIName = "");

/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
///
/// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
Expand Down
51 changes: 8 additions & 43 deletions llvm/lib/Target/ARM/ARMTargetMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -121,29 +121,10 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
return std::make_unique<ARMElfTargetObjectFile>();
}

static ARMBaseTargetMachine::ARMABI
computeTargetABI(const Triple &TT, StringRef CPU,
const TargetOptions &Options) {
StringRef ABIName = Options.MCOptions.getABIName();

if (ABIName.empty())
ABIName = ARM::computeDefaultTargetABI(TT, CPU);

if (ABIName == "aapcs16")
return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
else if (ABIName.starts_with("aapcs"))
return ARMBaseTargetMachine::ARM_ABI_AAPCS;
else if (ABIName.starts_with("apcs"))
return ARMBaseTargetMachine::ARM_ABI_APCS;

llvm_unreachable("Unhandled/unknown ABI Name!");
return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
}

static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options,
bool isLittle) {
auto ABI = computeTargetABI(TT, CPU, Options);
auto ABI = ARM::computeTargetABI(TT, CPU, Options.MCOptions.ABIName);
std::string Ret;

if (isLittle)
Expand All @@ -163,19 +144,19 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
Ret += "-Fi8";

// ABIs other than APCS have 64 bit integers with natural alignment.
if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
if (ABI != ARM::ARM_ABI_APCS)
Ret += "-i64:64";

// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
// bits, others to 64 bits. We always try to align to 64 bits.
if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
if (ABI == ARM::ARM_ABI_APCS)
Ret += "-f64:32:64";

// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
// to 64. We always ty to give them natural alignment.
if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
if (ABI == ARM::ARM_ABI_APCS)
Ret += "-v64:32:64-v128:32:128";
else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
else if (ABI != ARM::ARM_ABI_AAPCS16)
Ret += "-v128:64:128";

// Try to align aggregates to 32 bits (the default is 64 bits, which has no
Expand All @@ -187,9 +168,9 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,

// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
// aligned everywhere else.
if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
if (TT.isOSNaCl() || ABI == ARM::ARM_ABI_AAPCS16)
Ret += "-S128";
else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
else if (ABI == ARM::ARM_ABI_AAPCS)
Ret += "-S64";
else
Ret += "-S32";
Expand Down Expand Up @@ -226,7 +207,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TargetABI(computeTargetABI(TT, CPU, Options)),
TargetABI(ARM::computeTargetABI(TT, CPU, Options.MCOptions.ABIName)),
TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {

// Default to triple-appropriate float ABI
Expand Down Expand Up @@ -271,22 +252,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,

ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;

bool ARMBaseTargetMachine::isAPCS_ABI() const {
assert(TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
return TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
}

bool ARMBaseTargetMachine::isAAPCS_ABI() const {
assert(TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
return TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
}

bool ARMBaseTargetMachine::isAAPCS16_ABI() const {
assert(TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
return TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
}

MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
BumpPtrAllocator &Allocator, const Function &F,
const TargetSubtargetInfo *STI) const {
Expand Down
28 changes: 17 additions & 11 deletions llvm/lib/Target/ARM/ARMTargetMachine.h
Original file line number Diff line number Diff line change
Expand Up @@ -20,19 +20,15 @@
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/TargetParser/ARMTargetParser.h"
#include <memory>
#include <optional>

namespace llvm {

class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
public:
enum ARMABI {
ARM_ABI_UNKNOWN,
ARM_ABI_APCS,
ARM_ABI_AAPCS, // ARM EABI
ARM_ABI_AAPCS16
} TargetABI;
ARM::ARMABI TargetABI;

protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
Expand Down Expand Up @@ -66,9 +62,20 @@ class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
return TLOF.get();
}

bool isAPCS_ABI() const;
bool isAAPCS_ABI() const;
bool isAAPCS16_ABI() const;
bool isAPCS_ABI() const {
assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
return TargetABI == ARM::ARM_ABI_APCS;
}

bool isAAPCS_ABI() const {
assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
return TargetABI == ARM::ARM_ABI_AAPCS || TargetABI == ARM::ARM_ABI_AAPCS16;
}

bool isAAPCS16_ABI() const {
assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
return TargetABI == ARM::ARM_ABI_AAPCS16;
}

bool isTargetHardFloat() const {
return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
Expand All @@ -77,8 +84,7 @@ class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
TargetTriple.getEnvironment() == Triple::EABIHF ||
(TargetTriple.isOSBinFormatMachO() &&
TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||
TargetTriple.isOSWindows() ||
TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
TargetTriple.isOSWindows() || TargetABI == ARM::ARM_ABI_AAPCS16;
}

bool targetSchedulesPostRAScheduling() const override { return true; };
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ ARMElfTargetObjectFile::ARMElfTargetObjectFile() {
void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
const TargetMachine &TM) {
const ARMBaseTargetMachine &ARM_TM = static_cast<const ARMBaseTargetMachine &>(TM);
bool isAAPCS_ABI = ARM_TM.TargetABI == ARMBaseTargetMachine::ARMABI::ARM_ABI_AAPCS;
bool isAAPCS_ABI = ARM_TM.TargetABI == ARM::ARMABI::ARM_ABI_AAPCS;
bool genExecuteOnly =
ARM_TM.getMCSubtargetInfo()->hasFeature(ARM::FeatureExecuteOnly);

Expand Down
17 changes: 17 additions & 0 deletions llvm/lib/TargetParser/ARMTargetParser.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -575,6 +575,23 @@ StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
}
}

ARM::ARMABI ARM::computeTargetABI(const Triple &TT, StringRef CPU,
StringRef ABIName) {
if (ABIName.empty())
ABIName = ARM::computeDefaultTargetABI(TT, CPU);

if (ABIName == "aapcs16")
return ARM_ABI_AAPCS16;

if (ABIName.starts_with("aapcs"))
return ARM_ABI_AAPCS;

if (ABIName.starts_with("apcs"))
return ARM_ABI_APCS;

return ARM_ABI_UNKNOWN;
}

StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
if (MArch.empty())
MArch = Triple.getArchName();
Expand Down