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[X86] Remove extra MOV after widening atomic load #138635

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[X86] Remove extra MOV after widening atomic load #138635

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7 changes: 7 additions & 0 deletions llvm/lib/Target/X86/X86InstrCompiler.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1204,6 +1204,13 @@ def : Pat<(i16 (atomic_load_nonext_16 addr:$src)), (MOV16rm addr:$src)>;
def : Pat<(i32 (atomic_load_nonext_32 addr:$src)), (MOV32rm addr:$src)>;
def : Pat<(i64 (atomic_load_nonext_64 addr:$src)), (MOV64rm addr:$src)>;

def : Pat<(v4i32 (scalar_to_vector (i32 (zext (i16 (atomic_load_16 addr:$src)))))),
(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i8>
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this will dereference 32-bits

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@jofrn jofrn May 11, 2025 •
edited
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Switched it to a zext and now it dereferences 16 bits in the asm. Thanks.

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Next thing is to add SSE/AVX handling - I've added better test coverage at d27d0c7

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Without loss of generality, do we not need the v2 in --check-prefixes=CHECK,CHECKv2-O0 due to divergence of asm?

llvm-project/llvm/test/CodeGen/X86/atomic-load-store.ll

Line 7 in d27d0c7

; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -O0 -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,CHECK-O0

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Yes, you'll have to add extra check-prefixes - base + v2 can share CHECK-SSE-O* and v3/4 can share a CHECK-AVX-O* prefixes

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Ok. Thanks!

Since you've made the commits in already, I'll interleave the SSE/AVX updates throughout the series rather than making a new PR.

def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32 addr:$src)))),
(MOVDI2PDIrm addr:$src)>; // load atomic <2 x i16>
def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src)))),
(MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float>

// Floating point loads/stores.
def : Pat<(atomic_store_32 (i32 (bitconvert (f32 FR32:$src))), addr:$dst),
(MOVSSmr addr:$dst, FR32:$src)>, Requires<[UseSSE1]>;
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192 changes: 28 additions & 164 deletions llvm/test/CodeGen/X86/atomic-load-store.ll
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Expand Up @@ -319,159 +319,60 @@ define <2 x i8> @atomic_vec2_i8(ptr %x) {
define <2 x i16> @atomic_vec2_i16(ptr %x) {
; CHECK-O3-LABEL: atomic_vec2_i16:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movl (%rdi), %eax
; CHECK-O3-NEXT: movd %eax, %xmm0
; CHECK-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-O3-NEXT: retq
;
; CHECK-SSE-O3-LABEL: atomic_vec2_i16:
; CHECK-SSE-O3: # %bb.0:
; CHECK-SSE-O3-NEXT: movl (%rdi), %eax
; CHECK-SSE-O3-NEXT: movd %eax, %xmm0
; CHECK-SSE-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-SSE-O3-NEXT: retq
;
; CHECK-AVX-O3-LABEL: atomic_vec2_i16:
; CHECK-AVX-O3: # %bb.0:
; CHECK-AVX-O3-NEXT: movl (%rdi), %eax
; CHECK-AVX-O3-NEXT: vmovd %eax, %xmm0
; CHECK-AVX-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-AVX-O3-NEXT: retq
;
; CHECK-O0-LABEL: atomic_vec2_i16:
; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: movl (%rdi), %eax
; CHECK-O0-NEXT: movd %eax, %xmm0
; CHECK-O0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-O0-NEXT: retq
;
; CHECK-SSE-O0-LABEL: atomic_vec2_i16:
; CHECK-SSE-O0: # %bb.0:
; CHECK-SSE-O0-NEXT: movl (%rdi), %eax
; CHECK-SSE-O0-NEXT: movd %eax, %xmm0
; CHECK-SSE-O0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-SSE-O0-NEXT: retq
;
; CHECK-AVX-O0-LABEL: atomic_vec2_i16:
; CHECK-AVX-O0: # %bb.0:
; CHECK-AVX-O0-NEXT: movl (%rdi), %eax
; CHECK-AVX-O0-NEXT: vmovd %eax, %xmm0
; CHECK-AVX-O0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-AVX-O0-NEXT: retq
%ret = load atomic <2 x i16>, ptr %x acquire, align 4
ret <2 x i16> %ret
}

define <2 x ptr addrspace(270)> @atomic_vec2_ptr270(ptr %x) {
; CHECK-O3-LABEL: atomic_vec2_ptr270:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movq (%rdi), %rax
; CHECK-O3-NEXT: movq %rax, %xmm0
; CHECK-O3-NEXT: retq
;
; CHECK-SSE-O3-LABEL: atomic_vec2_ptr270:
; CHECK-SSE-O3: # %bb.0:
; CHECK-SSE-O3-NEXT: movq (%rdi), %rax
; CHECK-SSE-O3-NEXT: movq %rax, %xmm0
; CHECK-SSE-O3-NEXT: retq
;
; CHECK-AVX-O3-LABEL: atomic_vec2_ptr270:
; CHECK-AVX-O3: # %bb.0:
; CHECK-AVX-O3-NEXT: movq (%rdi), %rax
; CHECK-AVX-O3-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O3-NEXT: retq
;
; CHECK-O0-LABEL: atomic_vec2_ptr270:
; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: movq (%rdi), %rax
; CHECK-O0-NEXT: movq %rax, %xmm0
; CHECK-O0-NEXT: retq
;
; CHECK-SSE-O0-LABEL: atomic_vec2_ptr270:
; CHECK-SSE-O0: # %bb.0:
; CHECK-SSE-O0-NEXT: movq (%rdi), %rax
; CHECK-SSE-O0-NEXT: movq %rax, %xmm0
; CHECK-SSE-O0-NEXT: retq
;
; CHECK-AVX-O0-LABEL: atomic_vec2_ptr270:
; CHECK-AVX-O0: # %bb.0:
; CHECK-AVX-O0-NEXT: movq (%rdi), %rax
; CHECK-AVX-O0-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O0-NEXT: retq
; CHECK-LABEL: atomic_vec2_ptr270:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %xmm0
; CHECK-NEXT: retq
%ret = load atomic <2 x ptr addrspace(270)>, ptr %x acquire, align 8
ret <2 x ptr addrspace(270)> %ret
}

define <2 x i32> @atomic_vec2_i32_align(ptr %x) {
; CHECK-O3-LABEL: atomic_vec2_i32_align:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movq (%rdi), %rax
; CHECK-O3-NEXT: movq %rax, %xmm0
; CHECK-O3-NEXT: retq
;
; CHECK-SSE-O3-LABEL: atomic_vec2_i32_align:
; CHECK-SSE-O3: # %bb.0:
; CHECK-SSE-O3-NEXT: movq (%rdi), %rax
; CHECK-SSE-O3-NEXT: movq %rax, %xmm0
; CHECK-SSE-O3-NEXT: retq
;
; CHECK-AVX-O3-LABEL: atomic_vec2_i32_align:
; CHECK-AVX-O3: # %bb.0:
; CHECK-AVX-O3-NEXT: movq (%rdi), %rax
; CHECK-AVX-O3-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O3-NEXT: retq
;
; CHECK-O0-LABEL: atomic_vec2_i32_align:
; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: movq (%rdi), %rax
; CHECK-O0-NEXT: movq %rax, %xmm0
; CHECK-O0-NEXT: retq
;
; CHECK-SSE-O0-LABEL: atomic_vec2_i32_align:
; CHECK-SSE-O0: # %bb.0:
; CHECK-SSE-O0-NEXT: movq (%rdi), %rax
; CHECK-SSE-O0-NEXT: movq %rax, %xmm0
; CHECK-SSE-O0-NEXT: retq
;
; CHECK-AVX-O0-LABEL: atomic_vec2_i32_align:
; CHECK-AVX-O0: # %bb.0:
; CHECK-AVX-O0-NEXT: movq (%rdi), %rax
; CHECK-AVX-O0-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O0-NEXT: retq
; CHECK-LABEL: atomic_vec2_i32_align:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %xmm0
; CHECK-NEXT: retq
%ret = load atomic <2 x i32>, ptr %x acquire, align 8
ret <2 x i32> %ret
}

define <2 x float> @atomic_vec2_float_align(ptr %x) {
; CHECK-O3-LABEL: atomic_vec2_float_align:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movq (%rdi), %rax
; CHECK-O3-NEXT: movq %rax, %xmm0
; CHECK-O3-NEXT: retq
;
; CHECK-SSE-O3-LABEL: atomic_vec2_float_align:
; CHECK-SSE-O3: # %bb.0:
; CHECK-SSE-O3-NEXT: movq (%rdi), %rax
; CHECK-SSE-O3-NEXT: movq %rax, %xmm0
; CHECK-SSE-O3-NEXT: retq
;
; CHECK-AVX-O3-LABEL: atomic_vec2_float_align:
; CHECK-AVX-O3: # %bb.0:
; CHECK-AVX-O3-NEXT: movq (%rdi), %rax
; CHECK-AVX-O3-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O3-NEXT: retq
;
; CHECK-O0-LABEL: atomic_vec2_float_align:
; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: movq (%rdi), %rax
; CHECK-O0-NEXT: movq %rax, %xmm0
; CHECK-O0-NEXT: retq
;
; CHECK-SSE-O0-LABEL: atomic_vec2_float_align:
; CHECK-SSE-O0: # %bb.0:
; CHECK-SSE-O0-NEXT: movq (%rdi), %rax
; CHECK-SSE-O0-NEXT: movq %rax, %xmm0
; CHECK-SSE-O0-NEXT: retq
;
; CHECK-AVX-O0-LABEL: atomic_vec2_float_align:
; CHECK-AVX-O0: # %bb.0:
; CHECK-AVX-O0-NEXT: movq (%rdi), %rax
; CHECK-AVX-O0-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O0-NEXT: retq
; CHECK-LABEL: atomic_vec2_float_align:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %xmm0
; CHECK-NEXT: retq
%ret = load atomic <2 x float>, ptr %x acquire, align 8
ret <2 x float> %ret
}
Expand Down Expand Up @@ -900,79 +801,42 @@ define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {
define <4 x i8> @atomic_vec4_i8(ptr %x) nounwind {
; CHECK-O3-LABEL: atomic_vec4_i8:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movl (%rdi), %eax
; CHECK-O3-NEXT: movd %eax, %xmm0
; CHECK-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-O3-NEXT: retq
;
; CHECK-SSE-O3-LABEL: atomic_vec4_i8:
; CHECK-SSE-O3: # %bb.0:
; CHECK-SSE-O3-NEXT: movl (%rdi), %eax
; CHECK-SSE-O3-NEXT: movd %eax, %xmm0
; CHECK-SSE-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-SSE-O3-NEXT: retq
;
; CHECK-AVX-O3-LABEL: atomic_vec4_i8:
; CHECK-AVX-O3: # %bb.0:
; CHECK-AVX-O3-NEXT: movl (%rdi), %eax
; CHECK-AVX-O3-NEXT: vmovd %eax, %xmm0
; CHECK-AVX-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-AVX-O3-NEXT: retq
;
; CHECK-O0-LABEL: atomic_vec4_i8:
; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: movl (%rdi), %eax
; CHECK-O0-NEXT: movd %eax, %xmm0
; CHECK-O0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-O0-NEXT: retq
;
; CHECK-SSE-O0-LABEL: atomic_vec4_i8:
; CHECK-SSE-O0: # %bb.0:
; CHECK-SSE-O0-NEXT: movl (%rdi), %eax
; CHECK-SSE-O0-NEXT: movd %eax, %xmm0
; CHECK-SSE-O0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-SSE-O0-NEXT: retq
;
; CHECK-AVX-O0-LABEL: atomic_vec4_i8:
; CHECK-AVX-O0: # %bb.0:
; CHECK-AVX-O0-NEXT: movl (%rdi), %eax
; CHECK-AVX-O0-NEXT: vmovd %eax, %xmm0
; CHECK-AVX-O0-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-AVX-O0-NEXT: retq
%ret = load atomic <4 x i8>, ptr %x acquire, align 4
ret <4 x i8> %ret
}

define <4 x i16> @atomic_vec4_i16(ptr %x) nounwind {
; CHECK-O3-LABEL: atomic_vec4_i16:
; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movq (%rdi), %rax
; CHECK-O3-NEXT: movq %rax, %xmm0
; CHECK-O3-NEXT: retq
;
; CHECK-SSE-O3-LABEL: atomic_vec4_i16:
; CHECK-SSE-O3: # %bb.0:
; CHECK-SSE-O3-NEXT: movq (%rdi), %rax
; CHECK-SSE-O3-NEXT: movq %rax, %xmm0
; CHECK-SSE-O3-NEXT: retq
;
; CHECK-AVX-O3-LABEL: atomic_vec4_i16:
; CHECK-AVX-O3: # %bb.0:
; CHECK-AVX-O3-NEXT: movq (%rdi), %rax
; CHECK-AVX-O3-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O3-NEXT: retq
;
; CHECK-O0-LABEL: atomic_vec4_i16:
; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: movq (%rdi), %rax
; CHECK-O0-NEXT: movq %rax, %xmm0
; CHECK-O0-NEXT: retq
;
; CHECK-SSE-O0-LABEL: atomic_vec4_i16:
; CHECK-SSE-O0: # %bb.0:
; CHECK-SSE-O0-NEXT: movq (%rdi), %rax
; CHECK-SSE-O0-NEXT: movq %rax, %xmm0
; CHECK-SSE-O0-NEXT: retq
;
; CHECK-AVX-O0-LABEL: atomic_vec4_i16:
; CHECK-AVX-O0: # %bb.0:
; CHECK-AVX-O0-NEXT: movq (%rdi), %rax
; CHECK-AVX-O0-NEXT: vmovq %rax, %xmm0
; CHECK-AVX-O0-NEXT: retq
; CHECK-LABEL: atomic_vec4_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %xmm0
; CHECK-NEXT: retq
%ret = load atomic <4 x i16>, ptr %x acquire, align 8
ret <4 x i16> %ret
}
Expand Down
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