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[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills #129848

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Merged
merged 5 commits into from
Mar 18, 2025
Merged

[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills #129848

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ff029b6
[CodeGen] Utilizing register units based liveIns tracking
vg0204 Mar 5, 2025
6a7f07d
[AMDGPU][CodeGen] Utilized MBB's liveIn check in SILowerSGPRSpills
vg0204 Mar 5, 2025
0268630
Utilizing MCRegAliasIterator to check for all possible liveIn alias i…
vg0204 Mar 7, 2025
7901d5d
Moved isLiveIn check logic to a utility function
vg0204 Mar 17, 2025
b2f303e
Addressed reviewed changes in renaming utility fn
vg0204 Mar 18, 2025
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14 changes: 11 additions & 3 deletions llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -101,6 +101,16 @@ INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE,

char &llvm::SILowerSGPRSpillsLegacyID = SILowerSGPRSpillsLegacy::ID;

static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI) {
for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
if (MBB.isLiveIn(*R)) {
return true;
}
}
return false;
}

/// Insert spill code for the callee-saved registers used in the function.
static void insertCSRSaves(MachineBasicBlock &SaveBlock,
ArrayRef<CalleeSavedInfo> CSI, SlotIndexes *Indexes,
Expand All @@ -114,8 +124,6 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,

MachineBasicBlock::iterator I = SaveBlock.begin();
if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
const MachineRegisterInfo &MRI = MF.getRegInfo();

for (const CalleeSavedInfo &CS : CSI) {
// Insert the spill to the stack frame.
MCRegister Reg = CS.getReg();
Expand All @@ -128,7 +136,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
// incoming register value, so don't kill at the spill point. This happens
// since we pass some special inputs (workgroup IDs) in the callee saved
// range.
const bool IsLiveIn = MRI.isLiveIn(Reg);
const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, TRI);
TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
RC, TRI, Register());

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36 changes: 16 additions & 20 deletions llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
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Original file line number Diff line number Diff line change
@@ -1,25 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills %s -o /dev/null 2>&1 | FileCheck -check-prefix=VERIFIER %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s

# FIXME : Currently, MRI's liveIn check for registers does not take the corresponding live-in's sub-registers into account. As a result
# in SILowerSGPRSpills, the SubReg spill gets marked KILLED even though its SuperReg is in the function Live-ins. This causes machine
# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.

# VERIFIER: After SI lower SGPR spill instructions

# VERIFIER: *** Bad machine code: Using an undefined physical register ***
# VERIFIER: - instruction: S_NOP 0, implicit $sgpr50
# VERIFIER-NEXT: - operand 1: implicit $sgpr50

# VERIFIER: *** Bad machine code: Using an undefined physical register ***
# VERIFIER: - instruction: S_NOP 0, implicit $sgpr52
# VERIFIER-NEXT: - operand 1: implicit $sgpr52

# VERIFIER: *** Bad machine code: Using an undefined physical register ***
# VERIFIER: - instruction: S_NOP 0, implicit $sgpr55
# VERIFIER-NEXT: - operand 1: implicit $sgpr55

# VERIFIER: LLVM ERROR: Found 3 machine code errors.
---
name: spill_partial_live_csr_sgpr_test
tracksRegLiveness: true
Expand All @@ -31,6 +12,21 @@ body: |
bb.0:
liveins: $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55

; CHECK-LABEL: name: spill_partial_live_csr_sgpr_test
; CHECK: liveins: $sgpr50, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr63, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr52, 1, $vgpr63
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr53, 2, $vgpr63
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr54, 3, $vgpr63
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr55, 4, $vgpr63
; CHECK-NEXT: S_NOP 0, implicit $sgpr50
; CHECK-NEXT: $sgpr50 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit $sgpr52
; CHECK-NEXT: $sgpr52_sgpr53 = S_MOV_B64 0
; CHECK-NEXT: S_NOP 0, implicit $sgpr55
; CHECK-NEXT: $sgpr54_sgpr55 = S_MOV_B64 0
; CHECK-NEXT: $sgpr56 = S_MOV_B32 0
S_NOP 0, implicit $sgpr50
$sgpr50 = S_MOV_B32 0
S_NOP 0, implicit $sgpr52
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32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -55,22 +55,22 @@ body: |
; GCN-LABEL: name: sgpr_spill_lane_crossover
; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $vgpr63, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
; GCN-NEXT: {{ $}}
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr64, 0, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr65, 1, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr66, 2, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr67, 3, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr68, 4, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr69, 5, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr70, 6, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr71, 7, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr80, 8, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr81, 9, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr82, 10, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr83, 11, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr84, 12, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr85, 13, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr86, 14, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr87, 15, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, $vgpr63
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Losing these kill flags isn't ideal

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These are just another case mimicing the added test case accounting for this change!

; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr67, 3, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr68, 4, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr69, 5, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr70, 6, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr71, 7, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr80, 8, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr81, 9, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr82, 10, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr83, 11, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr84, 12, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr85, 13, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr86, 14, $vgpr63
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr87, 15, $vgpr63
; GCN-NEXT: S_NOP 0
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
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