[RISCV] Don't convert virtual register Register to MCRegister in isCompressibleInst. #122843
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…mpressibleInst. Calling MCRegisterClass::contains with a Register does an implicit conversion from Register to MCRegister. I think MCRegister is only intended to be used for physical registers. We should protect this implicit conversion by checking for physical registers first. While I was here I removed some unnecessary parentheses from the output.
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@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesCalling MCRegisterClass::contains with a Register does an implicit conversion from Register to MCRegister. I think MCRegister is only intended to be used for physical registers. We should protect this implicit conversion by checking for physical registers first. While I was here I removed some unnecessary parentheses from the output. Full diff: https://github.com/llvm/llvm-project/pull/122843.diff 2 Files Affected:
diff --git a/llvm/test/TableGen/AsmPredicateCombiningRISCV.td b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td
index 57ed00583db14c..56622e0f34e022 100644
--- a/llvm/test/TableGen/AsmPredicateCombiningRISCV.td
+++ b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td
@@ -60,23 +60,23 @@ def BigInst : RVInst<1, [AsmPred1]>;
def SmallInst1 : RVInst16<1, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
-// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
-// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
+// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
+// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst1 $r
def SmallInst2 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
-// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
-// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
+// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
+// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst2 $r
def SmallInst3 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
-// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
-// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
+// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
+// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst3 $r
def SmallInst4 : RVInst16<2, []>;
@@ -84,16 +84,16 @@ def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
-// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
-// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
+// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
+// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst4 $r
def SmallInst5 : RVInst16<2, []>;
def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
-// COMPRESS-NEXT: (MI.getOperand(0).isReg()) &&
-// COMPRESS-NEXT: (archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg()))) {
+// COMPRESS-NEXT: MI.getOperand(0).isReg() &&
+// COMPRESS-NEXT: archMCRegisterClasses[arch::RegsRegClassID].contains(MI.getOperand(0).getReg())) {
// COMPRESS-NEXT: // SmallInst5 $r
// COMPRESS-LABEL: static bool uncompressInst
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 7ebfe50a86d0fb..9e78abd7aad83a 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -773,13 +773,18 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
// This is a register operand. Check the register class.
// Don't check register class if this is a tied operand, it was done
// for the operand its tied to.
- if (DestOperand.getTiedRegister() == -1)
+ if (DestOperand.getTiedRegister() == -1) {
CondStream.indent(6)
- << "(MI.getOperand(" << OpIdx << ").isReg()) &&\n"
- << " (" << TargetName << "MCRegisterClasses[" << TargetName
+ << "MI.getOperand(" << OpIdx << ").isReg()";
+ if (EType == EmitterType::CheckCompress)
+ CondStream
+ << " && MI.getOperand(" << OpIdx << ").getReg().isPhysical()";
+ CondStream << " &&\n" << indent(6)
+ << TargetName << "MCRegisterClasses[" << TargetName
<< "::" << ClassRec->getName()
<< "RegClassID].contains(MI.getOperand(" << OpIdx
- << ").getReg())) &&\n";
+ << ").getReg()) &&\n";
+ }
if (CompressOrUncompress)
CodeStream.indent(6)
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✅ With the latest revision this PR passed the C/C++ code formatter. |
wangpc-pp
reviewed
Jan 14, 2025
| << "MI.getOperand(" << OpIdx << ").isReg()"; | ||
| if (EType == EmitterType::CheckCompress) | ||
| CondStream | ||
| << " && MI.getOperand(" << OpIdx << ").getReg().isPhysical()"; |
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No isPhysical in tests? Forgot to update tests? Or it is because there is no test coverage?
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We don't have a test for isCompressibleInst. The only .td test if is indirectly testing compressInst which operates on MCInst so its natively MCRegister, and MCRegister doesn't have isPhysical().
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We may just need to add some CHECKs?
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Calling MCRegisterClass::contains with a Register does an implicit conversion from Register to MCRegister. I think MCRegister is only intended to be used for physical registers. We should protect this implicit conversion by checking for physical registers first.
While I was here I removed some unnecessary parentheses from the output.