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[X86] Use loaded/stored element size when parsing/printing gather/scatter pointer size in Intel syntax. #122530

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Jan 13, 2025
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[X86] Use loaded/stored element size when parsing/printing gather/scatter pointer size in Intel syntax. #122530

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[X86] Use loaded/stored element size when parsing/printing gather/sca…
topperc Jan 10, 2025
1fb99a4
Merge remote-tracking branch 'origin/main' into pr/gather-scatter-size
topperc Jan 13, 2025
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46 changes: 19 additions & 27 deletions llvm/lib/Target/X86/AsmParser/X86Operand.h
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Expand Up @@ -340,46 +340,38 @@ struct X86Operand final : public MCParsedAsmOperand {
return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
}

bool isMem32_RC128() const {
return isMem32() && isMemIndexReg(X86::XMM0, X86::XMM15);
}
bool isMem64_RC128() const {
return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
}
bool isMem128_RC128() const {
return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15);
}
bool isMem128_RC256() const {
return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM15);
bool isMem32_RC256() const {
return isMem32() && isMemIndexReg(X86::YMM0, X86::YMM15);
}
bool isMem256_RC128() const {
return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15);
}
bool isMem256_RC256() const {
return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM15);
bool isMem64_RC256() const {
return isMem64() && isMemIndexReg(X86::YMM0, X86::YMM15);
}

bool isMem32_RC128X() const {
return isMem32() && X86II::isXMMReg(Mem.IndexReg);
}
bool isMem64_RC128X() const {
return isMem64() && X86II::isXMMReg(Mem.IndexReg);
}
bool isMem128_RC128X() const {
return isMem128() && X86II::isXMMReg(Mem.IndexReg);
bool isMem32_RC256X() const {
return isMem32() && X86II::isYMMReg(Mem.IndexReg);
}
bool isMem128_RC256X() const {
return isMem128() && X86II::isYMMReg(Mem.IndexReg);
bool isMem64_RC256X() const {
return isMem64() && X86II::isYMMReg(Mem.IndexReg);
}
bool isMem256_RC128X() const {
return isMem256() && X86II::isXMMReg(Mem.IndexReg);
bool isMem32_RC512() const {
return isMem32() && X86II::isZMMReg(Mem.IndexReg);
}
bool isMem256_RC256X() const {
return isMem256() && X86II::isYMMReg(Mem.IndexReg);
}
bool isMem256_RC512() const {
return isMem256() && X86II::isZMMReg(Mem.IndexReg);
}
bool isMem512_RC256X() const {
return isMem512() && X86II::isYMMReg(Mem.IndexReg);
}
bool isMem512_RC512() const {
return isMem512() && X86II::isZMMReg(Mem.IndexReg);
bool isMem64_RC512() const {
return isMem64() && X86II::isZMMReg(Mem.IndexReg);
}

bool isMem512_GR16() const {
if (!isMem512())
return false;
Expand Down
80 changes: 40 additions & 40 deletions llvm/lib/Target/X86/X86InstrAVX512.td
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Expand Up @@ -10279,36 +10279,36 @@ multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
defm NAME#D#SUFF#Z: avx512_gather<dopc, OpcodeStr#"d", _.info512,
vy512xmem>, EVEX_V512, REX_W;
vy64xmem>, EVEX_V512, REX_W;
defm NAME#Q#SUFF#Z: avx512_gather<qopc, OpcodeStr#"q", _.info512,
vz512mem>, EVEX_V512, REX_W;
vz64mem>, EVEX_V512, REX_W;
let Predicates = [HasVLX] in {
defm NAME#D#SUFF#Z256: avx512_gather<dopc, OpcodeStr#"d", _.info256,
vx256xmem>, EVEX_V256, REX_W;
vx64xmem>, EVEX_V256, REX_W;
defm NAME#Q#SUFF#Z256: avx512_gather<qopc, OpcodeStr#"q", _.info256,
vy256xmem>, EVEX_V256, REX_W;
vy64xmem>, EVEX_V256, REX_W;
defm NAME#D#SUFF#Z128: avx512_gather<dopc, OpcodeStr#"d", _.info128,
vx128xmem>, EVEX_V128, REX_W;
vx64xmem>, EVEX_V128, REX_W;
defm NAME#Q#SUFF#Z128: avx512_gather<qopc, OpcodeStr#"q", _.info128,
vx128xmem>, EVEX_V128, REX_W;
vx64xmem>, EVEX_V128, REX_W;
}
}

multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
defm NAME#D#SUFF#Z: avx512_gather<dopc, OpcodeStr#"d", _.info512, vz512mem>,
defm NAME#D#SUFF#Z: avx512_gather<dopc, OpcodeStr#"d", _.info512, vz32mem>,
EVEX_V512;
defm NAME#Q#SUFF#Z: avx512_gather<qopc, OpcodeStr#"q", _.info256, vz256mem>,
defm NAME#Q#SUFF#Z: avx512_gather<qopc, OpcodeStr#"q", _.info256, vz32mem>,
EVEX_V512;
let Predicates = [HasVLX] in {
defm NAME#D#SUFF#Z256: avx512_gather<dopc, OpcodeStr#"d", _.info256,
vy256xmem>, EVEX_V256;
vy32xmem>, EVEX_V256;
defm NAME#Q#SUFF#Z256: avx512_gather<qopc, OpcodeStr#"q", _.info128,
vy128xmem>, EVEX_V256;
vy32xmem>, EVEX_V256;
defm NAME#D#SUFF#Z128: avx512_gather<dopc, OpcodeStr#"d", _.info128,
vx128xmem>, EVEX_V128;
vx32xmem>, EVEX_V128;
defm NAME#Q#SUFF#Z128: avx512_gather<qopc, OpcodeStr#"q", _.info128,
vx64xmem, VK2WM>, EVEX_V128;
vx32xmem, VK2WM>, EVEX_V128;
}
}

Expand Down Expand Up @@ -10336,36 +10336,36 @@ let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain,
multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
defm NAME#D#SUFF#Z: avx512_scatter<dopc, OpcodeStr#"d", _.info512,
vy512xmem>, EVEX_V512, REX_W;
vy64xmem>, EVEX_V512, REX_W;
defm NAME#Q#SUFF#Z: avx512_scatter<qopc, OpcodeStr#"q", _.info512,
vz512mem>, EVEX_V512, REX_W;
vz64mem>, EVEX_V512, REX_W;
let Predicates = [HasVLX] in {
defm NAME#D#SUFF#Z256: avx512_scatter<dopc, OpcodeStr#"d", _.info256,
vx256xmem>, EVEX_V256, REX_W;
vx64xmem>, EVEX_V256, REX_W;
defm NAME#Q#SUFF#Z256: avx512_scatter<qopc, OpcodeStr#"q", _.info256,
vy256xmem>, EVEX_V256, REX_W;
vy64xmem>, EVEX_V256, REX_W;
defm NAME#D#SUFF#Z128: avx512_scatter<dopc, OpcodeStr#"d", _.info128,
vx128xmem>, EVEX_V128, REX_W;
vx64xmem>, EVEX_V128, REX_W;
defm NAME#Q#SUFF#Z128: avx512_scatter<qopc, OpcodeStr#"q", _.info128,
vx128xmem>, EVEX_V128, REX_W;
vx64xmem>, EVEX_V128, REX_W;
}
}

multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
defm NAME#D#SUFF#Z: avx512_scatter<dopc, OpcodeStr#"d", _.info512, vz512mem>,
defm NAME#D#SUFF#Z: avx512_scatter<dopc, OpcodeStr#"d", _.info512, vz32mem>,
EVEX_V512;
defm NAME#Q#SUFF#Z: avx512_scatter<qopc, OpcodeStr#"q", _.info256, vz256mem>,
defm NAME#Q#SUFF#Z: avx512_scatter<qopc, OpcodeStr#"q", _.info256, vz32mem>,
EVEX_V512;
let Predicates = [HasVLX] in {
defm NAME#D#SUFF#Z256: avx512_scatter<dopc, OpcodeStr#"d", _.info256,
vy256xmem>, EVEX_V256;
vy32xmem>, EVEX_V256;
defm NAME#Q#SUFF#Z256: avx512_scatter<qopc, OpcodeStr#"q", _.info128,
vy128xmem>, EVEX_V256;
vy32xmem>, EVEX_V256;
defm NAME#D#SUFF#Z128: avx512_scatter<dopc, OpcodeStr#"d", _.info128,
vx128xmem>, EVEX_V128;
vx32xmem>, EVEX_V128;
defm NAME#Q#SUFF#Z128: avx512_scatter<qopc, OpcodeStr#"q", _.info128,
vx64xmem, VK2WM>, EVEX_V128;
vx32xmem, VK2WM>, EVEX_V128;
}
}

Expand All @@ -10385,52 +10385,52 @@ multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeSt
}

defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK8WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vy64xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vz64mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK8WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vy64xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vz64mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK8WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vy64xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vz64mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
VK8WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;

defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vy64xmem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;
VK8WM, vz64mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>;

multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr, SchedWrite Sched> {
def rk : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
Expand Down
39 changes: 17 additions & 22 deletions llvm/lib/Target/X86/X86InstrOperands.td
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Expand Up @@ -25,20 +25,18 @@ let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in {
def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
// Gather mem operands
def X86Mem32_RC128Operand : AsmOperandClass { let Name = "Mem32_RC128"; }
def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; }
def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; }
def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; }
def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; }
def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; }
def X86Mem32_RC256Operand : AsmOperandClass { let Name = "Mem32_RC256"; }
def X86Mem64_RC256Operand : AsmOperandClass { let Name = "Mem64_RC256"; }

def X86Mem32_RC128XOperand : AsmOperandClass { let Name = "Mem32_RC128X"; }
def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; }
def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; }
def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; }
def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; }
def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; }
def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; }
def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; }
def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; }
def X86Mem32_RC256XOperand : AsmOperandClass { let Name = "Mem32_RC256X"; }
def X86Mem64_RC256XOperand : AsmOperandClass { let Name = "Mem64_RC256X"; }
def X86Mem32_RC512Operand : AsmOperandClass { let Name = "Mem32_RC512"; }
def X86Mem64_RC512Operand : AsmOperandClass { let Name = "Mem64_RC512"; }

def X86Mem512_GR16Operand : AsmOperandClass { let Name = "Mem512_GR16"; }
def X86Mem512_GR32Operand : AsmOperandClass { let Name = "Mem512_GR32"; }
def X86Mem512_GR64Operand : AsmOperandClass { let Name = "Mem512_GR64"; }
Expand Down Expand Up @@ -97,20 +95,17 @@ def i512mem_GR32 : X86MemOperand<"printzmmwordmem", X86Mem512_GR32Operand, 512>;
def i512mem_GR64 : X86MemOperand<"printzmmwordmem", X86Mem512_GR64Operand, 512>;

// Gather mem operands
def vx32mem : X86VMemOperand<VR128, "printdwordmem", X86Mem32_RC128Operand, 32>;
def vx64mem : X86VMemOperand<VR128, "printqwordmem", X86Mem64_RC128Operand, 64>;
def vx128mem : X86VMemOperand<VR128, "printxmmwordmem", X86Mem128_RC128Operand, 128>;
def vx256mem : X86VMemOperand<VR128, "printymmwordmem", X86Mem256_RC128Operand, 256>;
def vy128mem : X86VMemOperand<VR256, "printxmmwordmem", X86Mem128_RC256Operand, 128>;
def vy256mem : X86VMemOperand<VR256, "printymmwordmem", X86Mem256_RC256Operand, 256>;
def vy32mem : X86VMemOperand<VR256, "printdwordmem", X86Mem32_RC256Operand, 32>;
def vy64mem : X86VMemOperand<VR256, "printqwordmem", X86Mem64_RC256Operand, 64>;

def vx32xmem : X86VMemOperand<VR128X, "printdwordmem", X86Mem32_RC128XOperand, 32>;
def vx64xmem : X86VMemOperand<VR128X, "printqwordmem", X86Mem64_RC128XOperand, 64>;
def vx128xmem : X86VMemOperand<VR128X, "printxmmwordmem", X86Mem128_RC128XOperand, 128>;
def vx256xmem : X86VMemOperand<VR128X, "printymmwordmem", X86Mem256_RC128XOperand, 256>;
def vy128xmem : X86VMemOperand<VR256X, "printxmmwordmem", X86Mem128_RC256XOperand, 128>;
def vy256xmem : X86VMemOperand<VR256X, "printymmwordmem", X86Mem256_RC256XOperand, 256>;
def vy512xmem : X86VMemOperand<VR256X, "printzmmwordmem", X86Mem512_RC256XOperand, 512>;
def vz256mem : X86VMemOperand<VR512, "printymmwordmem", X86Mem256_RC512Operand, 256>;
def vz512mem : X86VMemOperand<VR512, "printzmmwordmem", X86Mem512_RC512Operand, 512>;
def vy32xmem : X86VMemOperand<VR256X, "printdwordmem", X86Mem32_RC256XOperand, 32>;
def vy64xmem : X86VMemOperand<VR256X, "printqwordmem", X86Mem64_RC256XOperand, 64>;
def vz32mem : X86VMemOperand<VR512, "printdwordmem", X86Mem32_RC512Operand, 32>;
def vz64mem : X86VMemOperand<VR512, "printqwordmem", X86Mem64_RC512Operand, 64>;

def shmem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>;
def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>;
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/X86/X86InstrSSE.td
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Expand Up @@ -8078,26 +8078,26 @@ let Predicates = [HasAVX2] in {
= "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
in {
defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq",
VR256, vx128mem, vx256mem>, REX_W;
VR256, vx64mem, vx64mem>, REX_W;
defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq",
VR256, vx128mem, vy256mem>, REX_W;
VR256, vx64mem, vy64mem>, REX_W;
defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd",
VR256, vx128mem, vy256mem>;
VR256, vx32mem, vy32mem>;
defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd",
VR128, vx64mem, vy128mem>;
VR128, vx32mem, vy32mem>;

let ExeDomain = SSEPackedDouble in {
defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd",
VR256, vx128mem, vx256mem>, REX_W;
VR256, vx64mem, vx64mem>, REX_W;
defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd",
VR256, vx128mem, vy256mem>, REX_W;
VR256, vx64mem, vy64mem>, REX_W;
}

let ExeDomain = SSEPackedSingle in {
defm VGATHERDPS : avx2_gather<0x92, "vgatherdps",
VR256, vx128mem, vy256mem>;
VR256, vx32mem, vy32mem>;
defm VGATHERQPS : avx2_gather<0x93, "vgatherqps",
VR128, vx64mem, vy128mem>;
VR128, vx32mem, vy32mem>;
}
}
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/Disassembler/X86/apx/evex-format.txt
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Expand Up @@ -90,7 +90,7 @@
## MRM5m

# ATT: vscatterpf0dps (%r16,%zmm0) {%k1}
# INTEL: vscatterpf0dps {k1}, zmmword ptr [r16 + zmm0]
# INTEL: vscatterpf0dps {k1}, dword ptr [r16 + zmm0]
0x62,0xfa,0x7d,0x49,0xc6,0x2c,0x00

# ATT: subq $127, 123(%r16), %r17
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/Disassembler/X86/intel-syntax.txt
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Expand Up @@ -108,10 +108,10 @@
# CHECK: vshufpd xmm0, xmm1, xmm2, 1
0xc5 0xf1 0xc6 0xc2 0x01

# CHECK: vpgatherqq ymm2, ymmword ptr [rdi + 2*ymm1], ymm0
# CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0
0xc4 0xe2 0xfd 0x91 0x14 0x4f

# CHECK: vpgatherdd xmm10, xmmword ptr [r15 + 2*xmm9], xmm8
# CHECK: vpgatherdd xmm10, dword ptr [r15 + 2*xmm9], xmm8
0xc4 0x02 0x39 0x90 0x14 0x4f

# CHECK: xsave64 [rax]
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