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[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. #120032

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Merged
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Dec 16, 2024
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[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. #120032

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29df9b2
[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP.
topperc Dec 16, 2024
64f0255
Merge remote-tracking branch 'origin/main' into pr/sext-icmp
topperc Dec 16, 2024
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15 changes: 11 additions & 4 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3077,10 +3077,17 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
if (TypeIdx == 0)
widenScalarDst(MI, WideTy);
else {
unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
MI.getOperand(1).getPredicate()))
? TargetOpcode::G_SEXT
: TargetOpcode::G_ZEXT;
LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
CmpInst::Predicate Pred =
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());

auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
unsigned ExtOpcode =
(CmpInst::isSigned(Pred) ||
TLI.isSExtCheaperThanZExt(getApproximateEVTForLLT(SrcTy, Ctx),
getApproximateEVTForLLT(WideTy, Ctx)))
? TargetOpcode::G_SEXT
: TargetOpcode::G_ZEXT;
widenScalarSrc(MI, WideTy, 2, ExtOpcode);
widenScalarSrc(MI, WideTy, 3, ExtOpcode);
}
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
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Expand Up @@ -215,8 +215,7 @@ define i32 @fneg_d(double %a, double %b) nounwind {
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: xor a1, a0, a1
; RV64I-NEXT: call __eqdf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down
30 changes: 9 additions & 21 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
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Expand Up @@ -117,25 +117,14 @@ define i32 @fcvt_wu_d(double %a) nounwind {
}

define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: bnez a0, .LBB4_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: li a0, 1
; RV32IFD-NEXT: .LBB4_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: slli a1, a0, 32
; RV64IFD-NEXT: srli a1, a1, 32
; RV64IFD-NEXT: bnez a1, .LBB4_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: li a0, 1
; RV64IFD-NEXT: .LBB4_2:
; RV64IFD-NEXT: ret
; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
; CHECKIFD-NEXT: bnez a0, .LBB4_2
; CHECKIFD-NEXT: # %bb.1:
; CHECKIFD-NEXT: li a0, 1
; CHECKIFD-NEXT: .LBB4_2:
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_d_multiple_use:
; RV32I: # %bb.0:
Expand All @@ -155,8 +144,7 @@ define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi
; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: bnez a1, .LBB4_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: li a0, 1
Expand Down
36 changes: 14 additions & 22 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
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Expand Up @@ -28,7 +28,7 @@ define i32 @fcmp_false(double %a, double %b) nounwind {
ret i32 %2
}

; FIXME: slli+srli on RV64 are unnecessary
; FIXME: slli+srli on RV64 are unnecessary
define i32 @fcmp_oeq(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fcmp_oeq:
; CHECKIFD: # %bb.0:
Expand All @@ -50,8 +50,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __eqdf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -194,7 +193,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind {
ret i32 %2
}

; FIXME: slli+srli on RV64 are unnecessary
; FIXME: slli+srli on RV64 are unnecessary
define i32 @fcmp_one(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fcmp_one:
; CHECKIFD: # %bb.0:
Expand Down Expand Up @@ -244,14 +243,12 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: call __eqdf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: and a0, s2, a0
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand All @@ -265,7 +262,7 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
ret i32 %2
}

; FIXME: slli+srli on RV64 are unnecessary
; FIXME: slli+srli on RV64 are unnecessary
define i32 @fcmp_ord(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fcmp_ord:
; CHECKIFD: # %bb.0:
Expand All @@ -289,8 +286,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -300,7 +296,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
ret i32 %2
}

; FIXME: slli+srli on RV64 are unnecessary
; FIXME: slli+srli on RV64 are unnecessary
define i32 @fcmp_ueq(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fcmp_ueq:
; CHECKIFD: # %bb.0:
Expand Down Expand Up @@ -351,14 +347,12 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: call __eqdf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: or a0, s2, a0
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -508,7 +502,7 @@ define i32 @fcmp_ule(double %a, double %b) nounwind {
ret i32 %2
}

; FIXME: slli+srli on RV64 are unnecessary
; FIXME: slli+srli on RV64 are unnecessary
define i32 @fcmp_une(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fcmp_une:
; CHECKIFD: # %bb.0:
Expand All @@ -531,8 +525,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __nedf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -542,7 +535,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
ret i32 %2
}

; FIXME: slli+srli on RV64 are unnecessary
; FIXME: slli+srli on RV64 are unnecessary
define i32 @fcmp_uno(double %a, double %b) nounwind {
; CHECKIFD-LABEL: fcmp_uno:
; CHECKIFD: # %bb.0:
Expand All @@ -567,8 +560,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
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Expand Up @@ -210,8 +210,7 @@ define i32 @fneg_s(float %a, float %b) nounwind {
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a1, a0, a1
; RV64I-NEXT: call __eqsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down
30 changes: 9 additions & 21 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
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Expand Up @@ -65,25 +65,14 @@ define i32 @fcvt_wu_s(float %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind {
; RV32IF-LABEL: fcvt_wu_s_multiple_use:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: bnez a0, .LBB2_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: .LBB2_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_multiple_use:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: slli a1, a0, 32
; RV64IF-NEXT: srli a1, a1, 32
; RV64IF-NEXT: bnez a1, .LBB2_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: .LBB2_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
; CHECKIF-NEXT: bnez a0, .LBB2_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: li a0, 1
; CHECKIF-NEXT: .LBB2_2:
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_multiple_use:
; RV32I: # %bb.0:
Expand All @@ -103,8 +92,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfsi
; RV64I-NEXT: slli a1, a0, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: bnez a1, .LBB2_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: li a0, 1
Expand Down
24 changes: 8 additions & 16 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
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Expand Up @@ -50,8 +50,7 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __eqsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -236,14 +235,12 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: call __eqsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __unordsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: and a0, s2, a0
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -281,8 +278,7 @@ define i32 @fcmp_ord(float %a, float %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __unordsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -335,14 +331,12 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: call __eqsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __unordsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: or a0, s2, a0
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -516,8 +510,7 @@ define i32 @fcmp_une(float %a, float %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __nesf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -552,8 +545,7 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __unordsf2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down
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