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[LoongArch] Use div.w/mod.w to eliminate unnecessary sign-extend for sdiv/srem i32. #117298

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Merged
merged 2 commits into from
Nov 27, 2024
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[LoongArch] Use div.w/mod.w to eliminate unnecessary sign-extend for sdiv/srem i32. #117298

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a6e2605
Use div.w/mod.w to eliminate unnecessary sign-extend instructions for…
tangaac Nov 22, 2024
50bc710
update test after rebase f4379db
tangaac Nov 27, 2024
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11 changes: 10 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -141,7 +141,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,

setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
setOperationAction(ISD::BSWAP, MVT::i32, Custom);
setOperationAction({ISD::UDIV, ISD::UREM}, MVT::i32, Custom);
setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, MVT::i32,
Custom);
setOperationAction(ISD::LROUND, MVT::i32, Custom);
}

Expand Down Expand Up @@ -2631,8 +2632,12 @@ static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unexpected opcode");
case ISD::SDIV:
return LoongArchISD::DIV_W;
case ISD::UDIV:
return LoongArchISD::DIV_WU;
case ISD::SREM:
return LoongArchISD::MOD_W;
case ISD::UREM:
return LoongArchISD::MOD_WU;
case ISD::SHL:
Expand Down Expand Up @@ -2829,7 +2834,9 @@ void LoongArchTargetLowering::ReplaceNodeResults(
"Unexpected custom legalisation");
Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
break;
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM:
assert(VT == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
Expand Down Expand Up @@ -4672,7 +4679,9 @@ const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(BITREV_W)
NODE_NAME_CASE(ROTR_W)
NODE_NAME_CASE(ROTL_W)
NODE_NAME_CASE(DIV_W)
NODE_NAME_CASE(DIV_WU)
NODE_NAME_CASE(MOD_W)
NODE_NAME_CASE(MOD_WU)
NODE_NAME_CASE(CLZ_W)
NODE_NAME_CASE(CTZ_W)
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.h
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Expand Up @@ -44,6 +44,8 @@ enum NodeType : unsigned {
ROTR_W,

// unsigned 32-bit integer division
DIV_W,
MOD_W,
DIV_WU,
MOD_WU,

Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
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Expand Up @@ -85,7 +85,9 @@ def loongarch_sll_w : SDNode<"LoongArchISD::SLL_W", SDT_LoongArchIntBinOpW>;
def loongarch_sra_w : SDNode<"LoongArchISD::SRA_W", SDT_LoongArchIntBinOpW>;
def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
def loongarch_div_w : SDNode<"LoongArchISD::DIV_W", SDT_LoongArchIntBinOpW>;
def loongarch_div_wu : SDNode<"LoongArchISD::DIV_WU", SDT_LoongArchIntBinOpW>;
def loongarch_mod_w : SDNode<"LoongArchISD::MOD_W", SDT_LoongArchIntBinOpW>;
def loongarch_mod_wu : SDNode<"LoongArchISD::MOD_WU", SDT_LoongArchIntBinOpW>;
def loongarch_crc_w_b_w
: SDNode<"LoongArchISD::CRC_W_B_W", SDT_LoongArchIntBinOpW, [SDNPHasChain]>;
Expand Down Expand Up @@ -1156,10 +1158,12 @@ def : PatGprGpr<sub, SUB_D>;
def : PatGprGpr<sdiv, DIV_D>;
def : PatGprGpr_32<sdiv, DIV_W>;
def : PatGprGpr<udiv, DIV_DU>;
def : PatGprGpr<loongarch_div_w, DIV_W>;
def : PatGprGpr<loongarch_div_wu, DIV_WU>;
def : PatGprGpr<srem, MOD_D>;
def : PatGprGpr_32<srem, MOD_W>;
def : PatGprGpr<urem, MOD_DU>;
def : PatGprGpr<loongarch_mod_w, MOD_W>;
def : PatGprGpr<loongarch_mod_wu, MOD_WU>;
def : PatGprGpr<shiftop<rotr>, ROTR_D>;
def : PatGprGpr<shiftopw<loongarch_rotr_w>, ROTR_W>;
Expand Down
18 changes: 6 additions & 12 deletions llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,21 +2,17 @@
; RUN: llc --mtriple=loongarch64 -mattr=+d,-div32 < %s | FileCheck %s --check-prefix=LA64
; RUN: llc --mtriple=loongarch64 -mattr=+d,+div32 < %s | FileCheck %s --check-prefix=LA64-DIV32

; TODO: Use div.w/mod.w for sdiv/srem i32

define i32 @divw(i64 %a, i64 %b) {
; LA64-LABEL: divw:
; LA64: # %bb.0:
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: addi.w $a1, $a1, 0
; LA64-NEXT: div.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: div.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA64-DIV32-LABEL: divw:
; LA64-DIV32: # %bb.0:
; LA64-DIV32-NEXT: addi.w $a0, $a0, 0
; LA64-DIV32-NEXT: addi.w $a1, $a1, 0
; LA64-DIV32-NEXT: div.d $a0, $a0, $a1
; LA64-DIV32-NEXT: div.w $a0, $a0, $a1
; LA64-DIV32-NEXT: ret
%conv1 = trunc i64 %a to i32
%conv2 = trunc i64 %b to i32
Expand Down Expand Up @@ -45,16 +41,14 @@ define i32 @divwu(i64 %a, i64 %b) {
define i32 @modw(i64 %a, i64 %b) {
; LA64-LABEL: modw:
; LA64: # %bb.0:
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: addi.w $a1, $a1, 0
; LA64-NEXT: mod.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: mod.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA64-DIV32-LABEL: modw:
; LA64-DIV32: # %bb.0:
; LA64-DIV32-NEXT: addi.w $a0, $a0, 0
; LA64-DIV32-NEXT: addi.w $a1, $a1, 0
; LA64-DIV32-NEXT: mod.d $a0, $a0, $a1
; LA64-DIV32-NEXT: mod.w $a0, $a0, $a1
; LA64-DIV32-NEXT: ret
%conv1 = trunc i64 %a to i32
%conv2 = trunc i64 %b to i32
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
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Expand Up @@ -121,7 +121,7 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.w $a1, $a1, 0
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: div.d $a0, $a0, $a1
; LA64-NEXT: div.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA32-TRAP-LABEL: sdiv_i32:
Expand All @@ -137,7 +137,7 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT: addi.w $a1, $a1, 0
; LA64-TRAP-NEXT: addi.w $a0, $a0, 0
; LA64-TRAP-NEXT: div.d $a0, $a0, $a1
; LA64-TRAP-NEXT: div.w $a0, $a0, $a1
; LA64-TRAP-NEXT: bnez $a1, .LBB3_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT: break 7
Expand All @@ -156,7 +156,7 @@ define i32 @sdiv_ui32_si32_si32(i32 signext %a, i32 signext %b) {
;
; LA64-LABEL: sdiv_ui32_si32_si32:
; LA64: # %bb.0: # %entry
; LA64-NEXT: div.d $a0, $a0, $a1
; LA64-NEXT: div.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA32-TRAP-LABEL: sdiv_ui32_si32_si32:
Expand All @@ -170,7 +170,7 @@ define i32 @sdiv_ui32_si32_si32(i32 signext %a, i32 signext %b) {
;
; LA64-TRAP-LABEL: sdiv_ui32_si32_si32:
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT: div.d $a0, $a0, $a1
; LA64-TRAP-NEXT: div.w $a0, $a0, $a1
; LA64-TRAP-NEXT: bnez $a1, .LBB4_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT: break 7
Expand Down Expand Up @@ -693,7 +693,7 @@ define i32 @srem_i32(i32 %a, i32 %b) {
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.w $a1, $a1, 0
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: mod.d $a0, $a0, $a1
; LA64-NEXT: mod.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA32-TRAP-LABEL: srem_i32:
Expand All @@ -709,7 +709,7 @@ define i32 @srem_i32(i32 %a, i32 %b) {
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT: addi.w $a1, $a1, 0
; LA64-TRAP-NEXT: addi.w $a0, $a0, 0
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
; LA64-TRAP-NEXT: bnez $a1, .LBB19_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT: break 7
Expand All @@ -728,7 +728,7 @@ define i32 @srem_ui32_si32_si32(i32 signext %a, i32 signext %b) {
;
; LA64-LABEL: srem_ui32_si32_si32:
; LA64: # %bb.0: # %entry
; LA64-NEXT: mod.d $a0, $a0, $a1
; LA64-NEXT: mod.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA32-TRAP-LABEL: srem_ui32_si32_si32:
Expand All @@ -742,7 +742,7 @@ define i32 @srem_ui32_si32_si32(i32 signext %a, i32 signext %b) {
;
; LA64-TRAP-LABEL: srem_ui32_si32_si32:
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
; LA64-TRAP-NEXT: bnez $a1, .LBB20_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT: break 7
Expand All @@ -763,7 +763,7 @@ define signext i32 @srem_si32_ui32_ui32(i32 %a, i32 %b) {
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.w $a1, $a1, 0
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: mod.d $a0, $a0, $a1
; LA64-NEXT: mod.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA32-TRAP-LABEL: srem_si32_ui32_ui32:
Expand All @@ -779,7 +779,7 @@ define signext i32 @srem_si32_ui32_ui32(i32 %a, i32 %b) {
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT: addi.w $a1, $a1, 0
; LA64-TRAP-NEXT: addi.w $a0, $a0, 0
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
; LA64-TRAP-NEXT: bnez $a1, .LBB21_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT: break 7
Expand All @@ -798,7 +798,7 @@ define signext i32 @srem_si32_si32_si32(i32 signext %a, i32 signext %b) {
;
; LA64-LABEL: srem_si32_si32_si32:
; LA64: # %bb.0: # %entry
; LA64-NEXT: mod.d $a0, $a0, $a1
; LA64-NEXT: mod.w $a0, $a0, $a1
; LA64-NEXT: ret
;
; LA32-TRAP-LABEL: srem_si32_si32_si32:
Expand All @@ -812,7 +812,7 @@ define signext i32 @srem_si32_si32_si32(i32 signext %a, i32 signext %b) {
;
; LA64-TRAP-LABEL: srem_si32_si32_si32:
; LA64-TRAP: # %bb.0: # %entry
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
; LA64-TRAP-NEXT: bnez $a1, .LBB22_2
; LA64-TRAP-NEXT: # %bb.1: # %entry
; LA64-TRAP-NEXT: break 7
Expand Down