[msan] Switch to -msan-handle-icmp-exact my default #113200
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Created using spr 1.3.4 [skip ci]
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@llvm/pr-subscribers-compiler-rt-sanitizer @llvm/pr-subscribers-llvm-transforms Author: Vitaly Buka (vitalybuka) ChangesFixes #111212. This grows .text by 5.3% on CTMark, (or 2.6% large internal binary) It worth to pay some performance regression to fix Patch is 49.51 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113200.diff 3 Files Affected:
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 9e174e2415e719..440413b8c2684f 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -276,7 +276,7 @@ static cl::opt<bool>
static cl::opt<bool>
ClHandleICmpExact("msan-handle-icmp-exact",
cl::desc("exact handling of relational integer ICmp"),
- cl::Hidden, cl::init(false));
+ cl::Hidden, cl::init(true));
static cl::opt<bool> ClHandleLifetimeIntrinsics(
"msan-handle-lifetime-intrinsics",
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
index 809e20dcb4a919..7aeb763b309048 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
@@ -1622,7 +1622,21 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
-; CHECK-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i32 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1
+; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp slt i32 [[TMP14]], 0
+; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = icmp slt i32 [[X]], 0
; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i1 [[TMP17]]
@@ -1632,7 +1646,21 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; ORIGIN-NEXT: call void @llvm.donothing()
-; ORIGIN-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1
+; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
+; ORIGIN-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0
+; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1
+; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
+; ORIGIN-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0
+; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
; ORIGIN-NEXT: [[TMP18:%.*]] = icmp slt i32 [[X]], 0
; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1643,7 +1671,21 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CALLS-NEXT: call void @llvm.donothing()
-; CALLS-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1
+; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
+; CALLS-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0
+; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1
+; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
+; CALLS-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0
+; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
; CALLS-NEXT: [[TMP18:%.*]] = icmp slt i32 [[X]], 0
; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
; CALLS-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1659,7 +1701,21 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
-; CHECK-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp sge i32 [[TMP7]], 0
+; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1
+; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP14]], 0
+; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i32 [[X]], 0
; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i1 [[TMP17]]
@@ -1669,7 +1725,21 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; ORIGIN-NEXT: call void @llvm.donothing()
-; ORIGIN-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1
+; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
+; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0
+; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1
+; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
+; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0
+; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
; ORIGIN-NEXT: [[TMP18:%.*]] = icmp sge i32 [[X]], 0
; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1680,7 +1750,21 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CALLS-NEXT: call void @llvm.donothing()
-; CALLS-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1
+; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
+; CALLS-NEXT: [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0
+; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1
+; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
+; CALLS-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0
+; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
; CALLS-NEXT: [[TMP18:%.*]] = icmp sge i32 [[X]], 0
; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
; CALLS-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1696,7 +1780,21 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
-; CHECK-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i32 0, [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1
+; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt i32 0, [[TMP14]]
+; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = icmp sgt i32 0, [[X]]
; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i1 [[TMP17]]
@@ -1706,10 +1804,26 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; ORIGIN-NEXT: call void @llvm.donothing()
-; ORIGIN-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1
+; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
+; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]]
+; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1
+; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
+; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]]
+; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; ORIGIN-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
+; ORIGIN-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
; ORIGIN-NEXT: [[TMP20:%.*]] = icmp sgt i32 0, [[X]]
; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; ORIGIN-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
+; ORIGIN-NEXT: store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
; ORIGIN-NEXT: ret i1 [[TMP20]]
;
; CALLS-LABEL: define zeroext i1 @ICmpSGTZero(
@@ -1717,10 +1831,26 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CALLS-NEXT: call void @llvm.donothing()
-; CALLS-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1
+; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
+; CALLS-NEXT: [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]]
+; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1
+; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
+; CALLS-NEXT: [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]]
+; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; CALLS-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
+; CALLS-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
; CALLS-NEXT: [[TMP20:%.*]] = icmp sgt i32 0, [[X]]
; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; CALLS-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
+; CALLS-NEXT: store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
; CALLS-NEXT: ret i1 [[TMP20]]
;
%1 = icmp sgt i32 0, %x
@@ -1733,7 +1863,21 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
-; CHECK-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp sle i32 0, [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1
+; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp sle i32 0, [[TMP14]]
+; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = icmp sle i32 0, [[X]]
; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i1 [[TMP17]]
@@ -1743,10 +1887,26 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; ORIGIN-NEXT: call void @llvm.donothing()
-; ORIGIN-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1
+; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
+; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sle i32 0, [[TMP8]]
+; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1
+; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
+; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sle i32 0, [[TMP15]]
+; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; ORIGIN-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
+; ORIGIN-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
; ORIGIN-NEXT: [[TMP20:%.*]] = icmp sle i32 0, [[X]]
; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; ORIGIN-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
+; ORIGIN-NEXT: store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
; ORIGIN-NEXT: ret i1 [[TMP20]]
;
; CALLS-LABEL: define zeroext i1 @ICmpSLEZero(
@@ -1754,10 +1914,26 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory
; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
; CALLS-NEXT: call void @llvm.donothing()
-; CALLS-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
+; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
+; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
+; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1
+; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
+; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
+; CALLS-NEXT: [[TMP9:%.*]] = icmp sle i32 0, [[TMP8]]
+; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1
+; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
+; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
+; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1
+; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
+; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
+; CALLS-NEXT: [[TMP16:%.*]] = icmp sle i32 0, [[TMP15]]
+; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; CALLS-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
+; CALLS-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
; CALLS-NEXT: [[TMP20:%.*]] = icmp sle i32 0, [[X]]
; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; CALLS-NEXT: store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
+; CALLS-NEXT: store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
; CALLS-NEXT: ret i1 [[TMP20]]
;
%1 = icmp sle i32 0, %x
@@ -1773,7 +1949,21 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
-; CHECK-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1
+; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]]
+; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i32 -1, [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1
+; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp slt i32 -1, [[TMP14]]
+; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = icmp slt i32 -1, [[X]]
; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i1 [[TMP17]]
@@ -1783,10 +1973,26 @@ define zeroext i1 @ICmpS...
[truncated]
|
Created using spr 1.3.4 [skip ci]
Created using spr 1.3.4 [skip ci]
Created using spr 1.3.4 [skip ci]
fmayer
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Created using spr 1.3.4 [skip ci]
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PR is to: 1. Simplify test update in #113200 2. Make tests more comprehensive, currently interesting cases looks very basic: ``` ; CHECK-LABEL: @ICmpSGTAllOnes ; CHECK: icmp slt ; CHECK-NOT: call void @__msan_warning ; CHECK: icmp sgt ; CHECK-NOT: call void @__msan_warning ; CHECK: ret i1 ```
Created using spr 1.3.4 [skip ci]
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This reverts commit 395093e.
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CTMark #113200 size overhead was 5.3%, now it's 4.7%. The patch affects only signed integers. https://alive2.llvm.org/ce/z/Lv5hyi * The patch replaces code which extracted sign bit, maximized/minimized it, then packed it back, with simple sign bit flip. The another way to think about transformation is as a subtraction of MIN_SINT from A/B. Then we map MIN_SINT to 0, 0 to -MIN_SINT, and MAX_SINT to MAX_UINT. * Then to maximize/minimize A/B we don't need to extract sign bit, we can apply shadow the same way as to other bits. * After sign bit flip, we had to switch to unsigned version of the predicates. * After change above getHighestPossibleValue/getLowestPossibleValue became very similar, so we can combine into a single function. * Because the function does sign bit flip and requires unsigned predicates used for returned values, there is no point in keeping it as a member of class, to hide, we switch to function local lambda.
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…lvm#111236) The underlying issue with msan was fixed by llvm#113200
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CTMark llvm#113200 size overhead was 5.3%, now it's 4.7%. The patch affects only signed integers. https://alive2.llvm.org/ce/z/Lv5hyi * The patch replaces code which extracted sign bit, maximized/minimized it, then packed it back, with simple sign bit flip. The another way to think about transformation is as a subtraction of MIN_SINT from A/B. Then we map MIN_SINT to 0, 0 to -MIN_SINT, and MAX_SINT to MAX_UINT. * Then to maximize/minimize A/B we don't need to extract sign bit, we can apply shadow the same way as to other bits. * After sign bit flip, we had to switch to unsigned version of the predicates. * After change above getHighestPossibleValue/getLowestPossibleValue became very similar, so we can combine into a single function. * Because the function does sign bit flip and requires unsigned predicates used for returned values, there is no point in keeping it as a member of class, to hide, we switch to function local lambda.
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Fixes #111212.
This grows .text by 5.3% on CTMark, (or 2.6% large internal binary)
Perf regressed by 1.6%. We will try to improve in follow up patches.
It worth to pay some performance regression to fix
correctness to avoid stuff like #111212.