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Fix build break when building RISCVInstrInfo.cpp with MSVC #110342

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Merged
merged 1 commit into from
Sep 30, 2024

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dpaoliello
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After #109774 MSVC is failing to build LLVM with the error:

llvm\lib\Target\RISCV\RISCVInstrInfo.cpp(782): warning C4018: '<': signed/unsigned mismatch

Fix is ensure that the RHS is an unsigned integer.

@llvmbot
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llvmbot commented Sep 27, 2024

@llvm/pr-subscribers-backend-risc-v

Author: Daniel Paoliello (dpaoliello)

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After #109774 MSVC is failing to build LLVM with the error:

llvm\lib\Target\RISCV\RISCVInstrInfo.cpp(782): warning C4018: '&lt;': signed/unsigned mismatch

Fix is ensure that the RHS is an unsigned integer.


Full diff: https://github.com/llvm/llvm-project/pull/110342.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+1-1)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index f0295d289ed86a..529944044f02d2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -779,7 +779,7 @@ MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
     if (RISCV::getRVVMCOpcode(MI.getOpcode()) == RISCV::VMV_X_S) {
       unsigned Log2SEW =
           MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
-      if (STI.getXLen() < (1 << Log2SEW))
+      if (STI.getXLen() < (1U << Log2SEW))
         return nullptr;
       switch (Log2SEW) {
       case 3:

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LGTM

@lukel97
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lukel97 commented Sep 29, 2024

Thanks for fixing this. What version of MSVC was this showing up with? This seemed to slip past the windows pre-merge CI: https://buildkite.com/llvm-project/github-pull-requests/builds/103512#0192235b-a71e-4dc7-8b7b-6ba3b185f6ac

@dpaoliello
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Looks like CI is running VS 2019:

The C compiler identification is MSVC 19.29.30154.0

And I'm using VS 2022:

> cl --version
Microsoft (R) C/C++ Optimizing Compiler Version 19.41.34120 for x64

@dpaoliello dpaoliello merged commit ce6369e into llvm:main Sep 30, 2024
8 of 10 checks passed
@dpaoliello dpaoliello deleted the riscvmsvc branch September 30, 2024 17:40
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4 participants