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[RISCV] Fold vfmv.f.s of f16 into load from stack #110214

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Merged
merged 3 commits into from
Oct 1, 2024
Merged

[RISCV] Fold vfmv.f.s of f16 into load from stack #110214

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4cb69a1
Precommit tests
lukel97 Sep 27, 2024
cdf9cb4
[RISCV] Fold vfmv.f.s of f16 into load from stack
lukel97 Sep 27, 2024
73ec586
Add RUN lines for illegal scalar types
lukel97 Sep 30, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -804,8 +804,8 @@ MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
switch (Log2SEW) {
case 4:
// TODO: Support f16/bf16
return nullptr;
LoadOpc = RISCV::FLH;
break;
case 5:
LoadOpc = RISCV::FLW;
break;
Expand Down
135 changes: 133 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/stack-folding.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV64 %s
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfbfmin,+zvfh,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV32,ZFMIN %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfbfmin,+zvfh,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV64,ZFMIN %s
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV32,NOZFMIN %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV64,NOZFMIN %s

define i64 @i64(<vscale x 1 x i64> %v, i1 %c) {
; RV32-LABEL: i64:
Expand Down Expand Up @@ -257,3 +259,132 @@ falsebb:
ret float 0.0
}

define half @f16(<vscale x 1 x half> %v, i1 %c) {
; ZFMIN-LABEL: f16:
; ZFMIN: # %bb.0:
; ZFMIN-NEXT: addi sp, sp, -16
; ZFMIN-NEXT: .cfi_def_cfa_offset 16
; ZFMIN-NEXT: csrr a1, vlenb
; ZFMIN-NEXT: slli a1, a1, 1
; ZFMIN-NEXT: sub sp, sp, a1
; ZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; ZFMIN-NEXT: addi a1, sp, 16
; ZFMIN-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; ZFMIN-NEXT: andi a0, a0, 1
; ZFMIN-NEXT: #APP
; ZFMIN-NEXT: #NO_APP
; ZFMIN-NEXT: beqz a0, .LBB6_2
; ZFMIN-NEXT: # %bb.1: # %truebb
; ZFMIN-NEXT: flh fa0, 16(sp) # 8-byte Folded Reload
; ZFMIN-NEXT: j .LBB6_3
; ZFMIN-NEXT: .LBB6_2: # %falsebb
; ZFMIN-NEXT: fmv.h.x fa0, zero
; ZFMIN-NEXT: .LBB6_3: # %falsebb
; ZFMIN-NEXT: csrr a0, vlenb
; ZFMIN-NEXT: slli a0, a0, 1
; ZFMIN-NEXT: add sp, sp, a0
; ZFMIN-NEXT: addi sp, sp, 16
; ZFMIN-NEXT: ret
;
; NOZFMIN-LABEL: f16:
; NOZFMIN: # %bb.0:
; NOZFMIN-NEXT: addi sp, sp, -16
; NOZFMIN-NEXT: .cfi_def_cfa_offset 16
; NOZFMIN-NEXT: csrr a1, vlenb
; NOZFMIN-NEXT: slli a1, a1, 1
; NOZFMIN-NEXT: sub sp, sp, a1
; NOZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; NOZFMIN-NEXT: addi a1, sp, 16
; NOZFMIN-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; NOZFMIN-NEXT: andi a0, a0, 1
; NOZFMIN-NEXT: #APP
; NOZFMIN-NEXT: #NO_APP
; NOZFMIN-NEXT: beqz a0, .LBB6_2
; NOZFMIN-NEXT: # %bb.1: # %truebb
; NOZFMIN-NEXT: lh a0, 16(sp) # 8-byte Folded Reload
; NOZFMIN-NEXT: lui a1, 1048560
; NOZFMIN-NEXT: or a0, a0, a1
; NOZFMIN-NEXT: j .LBB6_3
; NOZFMIN-NEXT: .LBB6_2: # %falsebb
; NOZFMIN-NEXT: lui a0, 1048560
; NOZFMIN-NEXT: .LBB6_3: # %falsebb
; NOZFMIN-NEXT: fmv.w.x fa0, a0
; NOZFMIN-NEXT: csrr a0, vlenb
; NOZFMIN-NEXT: slli a0, a0, 1
; NOZFMIN-NEXT: add sp, sp, a0
; NOZFMIN-NEXT: addi sp, sp, 16
; NOZFMIN-NEXT: ret
tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
br i1 %c, label %truebb, label %falsebb
truebb:
%x = extractelement <vscale x 1 x half> %v, i32 0
ret half %x
falsebb:
ret half 0.0
}

define bfloat @bf16(<vscale x 2 x bfloat> %v, i1 %c) {
; ZFMIN-LABEL: bf16:
; ZFMIN: # %bb.0:
; ZFMIN-NEXT: addi sp, sp, -16
; ZFMIN-NEXT: .cfi_def_cfa_offset 16
; ZFMIN-NEXT: csrr a1, vlenb
; ZFMIN-NEXT: slli a1, a1, 1
; ZFMIN-NEXT: sub sp, sp, a1
; ZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; ZFMIN-NEXT: addi a1, sp, 16
; ZFMIN-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; ZFMIN-NEXT: andi a0, a0, 1
; ZFMIN-NEXT: #APP
; ZFMIN-NEXT: #NO_APP
; ZFMIN-NEXT: beqz a0, .LBB7_2
; ZFMIN-NEXT: # %bb.1: # %truebb
; ZFMIN-NEXT: lh a0, 16(sp) # 8-byte Folded Reload
; ZFMIN-NEXT: fmv.h.x fa0, a0
; ZFMIN-NEXT: j .LBB7_3
; ZFMIN-NEXT: .LBB7_2: # %falsebb
; ZFMIN-NEXT: fmv.h.x fa0, zero
; ZFMIN-NEXT: .LBB7_3: # %falsebb
; ZFMIN-NEXT: csrr a0, vlenb
; ZFMIN-NEXT: slli a0, a0, 1
; ZFMIN-NEXT: add sp, sp, a0
; ZFMIN-NEXT: addi sp, sp, 16
; ZFMIN-NEXT: ret
;
; NOZFMIN-LABEL: bf16:
; NOZFMIN: # %bb.0:
; NOZFMIN-NEXT: addi sp, sp, -16
; NOZFMIN-NEXT: .cfi_def_cfa_offset 16
; NOZFMIN-NEXT: csrr a1, vlenb
; NOZFMIN-NEXT: slli a1, a1, 1
; NOZFMIN-NEXT: sub sp, sp, a1
; NOZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; NOZFMIN-NEXT: addi a1, sp, 16
; NOZFMIN-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
; NOZFMIN-NEXT: andi a0, a0, 1
; NOZFMIN-NEXT: #APP
; NOZFMIN-NEXT: #NO_APP
; NOZFMIN-NEXT: beqz a0, .LBB7_2
; NOZFMIN-NEXT: # %bb.1: # %truebb
; NOZFMIN-NEXT: lh a0, 16(sp) # 8-byte Folded Reload
; NOZFMIN-NEXT: lui a1, 1048560
; NOZFMIN-NEXT: or a0, a0, a1
; NOZFMIN-NEXT: j .LBB7_3
; NOZFMIN-NEXT: .LBB7_2: # %falsebb
; NOZFMIN-NEXT: lui a0, 1048560
; NOZFMIN-NEXT: .LBB7_3: # %falsebb
; NOZFMIN-NEXT: fmv.w.x fa0, a0
; NOZFMIN-NEXT: csrr a0, vlenb
; NOZFMIN-NEXT: slli a0, a0, 1
; NOZFMIN-NEXT: add sp, sp, a0
; NOZFMIN-NEXT: addi sp, sp, 16
; NOZFMIN-NEXT: ret
tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
br i1 %c, label %truebb, label %falsebb
truebb:
%x = extractelement <vscale x 2 x bfloat> %v, i32 0
ret bfloat %x
falsebb:
ret bfloat 0.0
}

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