[TargetLowering][SelectionDAG] Exploit nneg Flag in UINT_TO_FP #108931

mmarjieh · 2024-09-17T05:49:49Z

Propagate the nneg flag in WidenVecRes
Use SINT_TO_FP in expandUINT_TO_FP when possible.

llvmbot · 2024-09-17T05:50:21Z

@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-llvm-selectiondag

Author: Michael Marjieh (mmarjieh)

Changes

Propogate the nneg flag in WidenVecRes
Use SINT_TO_FP in expandUINT_TO_FP when possible.

Full diff: https://github.com/llvm/llvm-project/pull/108931.diff

3 Files Affected:

(modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+5-5)
(modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+14-6)
(modified) llvm/test/CodeGen/VE/Scalar/cast.ll (+10)

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 482f88e5c86de7..249cda171fbbf0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -5205,7 +5205,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
   if (N->getOpcode() == ISD::ZERO_EXTEND &&
       getTypeAction(InVT) == TargetLowering::TypePromoteInteger &&
       TLI.getTypeToTransformTo(Ctx, InVT).getScalarSizeInBits() !=
-      WidenVT.getScalarSizeInBits()) {
+          WidenVT.getScalarSizeInBits()) {
     InOp = ZExtPromotedInteger(InOp);
     InVT = InOp.getValueType();
     if (WidenVT.getScalarSizeInBits() < InVT.getScalarSizeInBits())
@@ -5222,7 +5222,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
     InVTEC = InVT.getVectorElementCount();
     if (InVTEC == WidenEC) {
       if (N->getNumOperands() == 1)
-        return DAG.getNode(Opcode, DL, WidenVT, InOp);
+        return DAG.getNode(Opcode, DL, WidenVT, InOp, Flags);
       if (N->getNumOperands() == 3) {
         assert(N->isVPOpcode() && "Expected VP opcode");
         SDValue Mask =
@@ -5258,7 +5258,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
       Ops[0] = InOp;
       SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
       if (N->getNumOperands() == 1)
-        return DAG.getNode(Opcode, DL, WidenVT, InVec);
+        return DAG.getNode(Opcode, DL, WidenVT, InVec, Flags);
       return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
     }
 
@@ -5267,7 +5267,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
                                   DAG.getVectorIdxConstant(0, DL));
       // Extract the input and convert the shorten input vector.
       if (N->getNumOperands() == 1)
-        return DAG.getNode(Opcode, DL, WidenVT, InVal);
+        return DAG.getNode(Opcode, DL, WidenVT, InVal, Flags);
       return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
     }
   }
@@ -5282,7 +5282,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
     SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
                               DAG.getVectorIdxConstant(i, DL));
     if (N->getNumOperands() == 1)
-      Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
+      Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, Flags);
     else
       Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
   }
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 95937886280685..0522958d5221c1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8361,18 +8361,26 @@ bool TargetLowering::expandFP_TO_UINT(SDNode *Node, SDValue &Result,
 }
 
 bool TargetLowering::expandUINT_TO_FP(SDNode *Node, SDValue &Result,
-                                      SDValue &Chain,
-                                      SelectionDAG &DAG) const {
+                                      SDValue &Chain, SelectionDAG &DAG) const {
+  SDValue Src = Node->getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  EVT DstVT = Node->getValueType(0);
+
+  // If the input is known to be non-negative and SINT_TO_FP is legal then use
+  // it.
+  if (Node->getFlags().hasNonNeg() &&
+      isOperationLegalOrCustom(ISD::SINT_TO_FP, DstVT)) {
+    Result =
+        DAG.getNode(ISD::SINT_TO_FP, SDLoc(Node), DstVT, Node->getOperand(0));
+    return true;
+  }
+
   // This transform is not correct for converting 0 when rounding mode is set
   // to round toward negative infinity which will produce -0.0. So disable under
   // strictfp.
   if (Node->isStrictFPOpcode())
     return false;
 
-  SDValue Src = Node->getOperand(0);
-  EVT SrcVT = Src.getValueType();
-  EVT DstVT = Node->getValueType(0);
-
   if (SrcVT.getScalarType() != MVT::i64 || DstVT.getScalarType() != MVT::f64)
     return false;
 
diff --git a/llvm/test/CodeGen/VE/Scalar/cast.ll b/llvm/test/CodeGen/VE/Scalar/cast.ll
index 44782b342f4d0f..9253b5591b351d 100644
--- a/llvm/test/CodeGen/VE/Scalar/cast.ll
+++ b/llvm/test/CodeGen/VE/Scalar/cast.ll
@@ -568,6 +568,16 @@ define float @ull2f(i64 %x) {
   ret float %r
 }
 
+define float @ull2f_nneg(i64 %x) {
+; CHECK-LABEL: ull2f_nneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cvt.d.l %s0, %s0
+; CHECK-NEXT:    cvt.s.d %s0, %s0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %r = uitofp nneg i64 %x to float
+  ret float %r
+}
+
 define double @ull2d(i64 %x) {
 ; CHECK-LABEL: ull2d:
 ; CHECK:       # %bb.0:

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

arsenm · 2024-09-18T09:03:22Z

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

+  // If the input is known to be non-negative and SINT_TO_FP is legal then use
+  // it.
+  if (Node->getFlags().hasNonNeg() &&
+      isOperationLegalOrCustom(ISD::SINT_TO_FP, DstVT)) {


SINT_TO_FP is one of the opcodes that checks the legality based on the source type, not the result type. This is bad because you really need to know both types

What do you suggest?
isOperationLegalOrCustom(ISD::SINT_TO_FP, SrcVT))
?

Yes, that is what the legalizer actually checks:

llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Line 1012 in 556ec4a

Node->getOperand(0).getValueType());

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

arsenm · 2024-10-01T09:11:13Z

llvm/test/CodeGen/VE/Scalar/cast.ll

+  %r = uitofp nneg i64 %x to float
+  ret float %r
+}
+


Missing vector tests? Can you also add strictfp tests?

I can't find a target that has uitofp marked as Expand and sitofp marked as legal or custom on vector types.
I added a strictfp.

mmarjieh · 2024-10-14T08:42:24Z

@arsenm Can you submit it on my behalf? I don't have write access.

Squashed Commit Message:
[TargetLowering][SelectionDAG] Exploit nneg Flag in UINT_TO_FP

Propogate the nneg flag in WidenVecRes
Use SINT_TO_FP in expandUINT_TO_FP when possible.

arsenm · 2024-10-14T08:43:28Z

You can just edit the commit description directly?

mmarjieh · 2024-10-14T08:53:17Z

You can just edit the commit description directly?
@arsenm
If I remember correctly, the should be an option to squash the commits, don't you have it near the merge button?

1. Propogate the nneg flag in WidenVecRes 2. Use SINT_TO_FP in expandUINT_TO_FP when possible.

arsenm · 2024-10-14T12:24:51Z

You can just edit the commit description directly?
@llvm/pr-subscribers-openmp

If I remember correctly, the should be an option to squash the commits, don't you have it near the merge button?

That is the only option enabled for the llvm repo

mmarjieh · 2024-10-14T18:21:33Z

@arsenm I appreciate your help, thanks!

…108931) 1. Propagate the nneg flag in WidenVecRes 2. Use SINT_TO_FP in expandUINT_TO_FP when possible.

llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Sep 17, 2024

komalon1 requested review from arsenm, RKSimon and topperc September 17, 2024 06:11

RKSimon reviewed Sep 17, 2024

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Show resolved Hide resolved

arsenm reviewed Sep 18, 2024

View reviewed changes

mmarjieh force-pushed the main branch from 31bde04 to 92af8b4 Compare September 25, 2024 15:35

arsenm reviewed Oct 1, 2024

View reviewed changes

llvmbot added the backend:X86 label Oct 14, 2024

arsenm approved these changes Oct 14, 2024

View reviewed changes

mmarjieh force-pushed the main branch from 9e7ad9b to 0bbd2ec Compare October 14, 2024 08:51

mmarjieh added 3 commits October 14, 2024 13:27

[TargetLowering][SelectionDAG] Exploit nneg Flag in UINT_TO_FP

84d910d

1. Propogate the nneg flag in WidenVecRes 2. Use SINT_TO_FP in expandUINT_TO_FP when possible.

Fix One More Comment

f822d0c

Add Test and Fix Strict Ops

50c4ae6

mmarjieh force-pushed the main branch from 0bbd2ec to 50c4ae6 Compare October 14, 2024 10:27

arsenm added 2 commits October 14, 2024 16:25

Merge branch 'main' into main

2e1f8fd

Merge branch 'main' into main

973d78c

arsenm merged commit b5600c6 into llvm:main Oct 14, 2024
8 checks passed

DanielCChen pushed a commit to DanielCChen/llvm-project that referenced this pull request Oct 16, 2024

[TargetLowering][SelectionDAG] Exploit nneg Flag in UINT_TO_FP (llvm#…

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…108931) 1. Propagate the nneg flag in WidenVecRes 2. Use SINT_TO_FP in expandUINT_TO_FP when possible.

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