[TTI][RISCV] Unconditionally break critical edges to sink ADDI

llvm/include/llvm/CodeGen/TargetInstrInfo.h

@@ -159,6 +159,12 @@ class TargetInstrInfo : public MCInstrInfo {
     return true;
   }
 
+  /// For a "cheap" instruction which doesn't enable additional sinking,
+  /// should MachineSink break a critical edge to sink it anyways?
+  virtual bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const {
+    return false;
+  }
+
 protected:
   /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
   /// set, this hook lets the target specify whether the instruction is actually

llvm/lib/CodeGen/MachineSink.cpp

@@ -958,7 +958,9 @@ bool MachineSinking::isWorthBreakingCriticalEdge(
     }
   }
 
-  return false;
+  // Let the target decide if it's worth breaking this
+  // critical edge for a "cheap" instruction.
+  return TII->shouldBreakCriticalEdgeToSink(MI);
 }
 
 bool MachineSinking::isLegalToBreakCriticalEdge(MachineInstr &MI,

llvm/lib/Target/RISCV/RISCVInstrInfo.h

@@ -78,6 +78,11 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
 
+  bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
+    return MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
+           MI.getOperand(1).getReg() == RISCV::X0;
+  }
+
   void copyPhysRegVector(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
                          MCRegister DstReg, MCRegister SrcReg, bool KillSrc,

llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll

@@ -43,23 +43,21 @@ define i32 @fcvt_wu_d(double %a) nounwind {
 define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
 ; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV32IFD-NEXT:    li a0, 1
-; RV32IFD-NEXT:    beqz a1, .LBB4_2
+; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV32IFD-NEXT:    bnez a0, .LBB4_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    mv a0, a1
+; RV32IFD-NEXT:    li a0, 1
 ; RV32IFD-NEXT:  .LBB4_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; RV64IFD-NEXT:    slli a0, a1, 32
-; RV64IFD-NEXT:    srli a2, a0, 32
-; RV64IFD-NEXT:    li a0, 1
-; RV64IFD-NEXT:    beqz a2, .LBB4_2
+; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV64IFD-NEXT:    slli a1, a0, 32
+; RV64IFD-NEXT:    srli a1, a1, 32
+; RV64IFD-NEXT:    bnez a1, .LBB4_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    mv a0, a1
+; RV64IFD-NEXT:    li a0, 1
 ; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    ret
   %a = fptoui double %x to i32

llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll

@@ -27,23 +27,21 @@ define i32 @fcvt_wu_s(float %a) nounwind {
 define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind {
 ; RV32IF-LABEL: fcvt_wu_s_multiple_use:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV32IF-NEXT:    li a0, 1
-; RV32IF-NEXT:    beqz a1, .LBB2_2
+; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV32IF-NEXT:    bnez a0, .LBB2_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    mv a0, a1
+; RV32IF-NEXT:    li a0, 1
 ; RV32IF-NEXT:  .LBB2_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_wu_s_multiple_use:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; RV64IF-NEXT:    slli a0, a1, 32
-; RV64IF-NEXT:    srli a2, a0, 32
-; RV64IF-NEXT:    li a0, 1
-; RV64IF-NEXT:    beqz a2, .LBB2_2
+; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV64IF-NEXT:    slli a1, a0, 32
+; RV64IF-NEXT:    srli a1, a1, 32
+; RV64IF-NEXT:    bnez a1, .LBB2_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    mv a0, a1
+; RV64IF-NEXT:    li a0, 1
 ; RV64IF-NEXT:  .LBB2_2:
 ; RV64IF-NEXT:    ret
   %a = fptoui float %x to i32

llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll

@@ -196,11 +196,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
 define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: findLastSet_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -32
-; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    li s0, -1
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a1, a0, 32
 ; RV64I-NEXT:    srliw a2, a0, 1
 ; RV64I-NEXT:    lui a3, 349525
@@ -227,36 +225,37 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
 ; RV64I-NEXT:    srli a2, a0, 4
 ; RV64I-NEXT:    add a0, a2, a0
 ; RV64I-NEXT:    lui a2, 4112
-; RV64I-NEXT:    srli s1, a1, 32
+; RV64I-NEXT:    srli s0, a1, 32
 ; RV64I-NEXT:    addiw a1, a3, -241
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    addiw a1, a2, 257
 ; RV64I-NEXT:    call __muldi3
-; RV64I-NEXT:    beqz s1, .LBB3_2
+; RV64I-NEXT:    beqz s0, .LBB3_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    srliw a0, a0, 24
 ; RV64I-NEXT:    li a1, 32
 ; RV64I-NEXT:    subw a1, a1, a0
-; RV64I-NEXT:    xori s0, a1, 31
+; RV64I-NEXT:    xori a0, a1, 31
+; RV64I-NEXT:    j .LBB3_3
 ; RV64I-NEXT:  .LBB3_2:
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:  .LBB3_3:
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findLastSet_i32:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    slli a1, a0, 32
-; RV64ZBB-NEXT:    srli a2, a1, 32
-; RV64ZBB-NEXT:    li a1, -1
-; RV64ZBB-NEXT:    beqz a2, .LBB3_2
+; RV64ZBB-NEXT:    srli a1, a1, 32
+; RV64ZBB-NEXT:    beqz a1, .LBB3_2
 ; RV64ZBB-NEXT:  # %bb.1:
 ; RV64ZBB-NEXT:    clzw a0, a0
-; RV64ZBB-NEXT:    xori a1, a0, 31
+; RV64ZBB-NEXT:    xori a0, a0, 31
+; RV64ZBB-NEXT:    ret
 ; RV64ZBB-NEXT:  .LBB3_2:
-; RV64ZBB-NEXT:    mv a0, a1
+; RV64ZBB-NEXT:    li a0, -1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
   %2 = xor i32 31, %1
@@ -493,14 +492,12 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
 define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: findFirstSet_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi sp, sp, -32
-; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    li s0, -1
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    addi a1, s1, -1
+; RV64I-NEXT:    addi a1, s0, -1
 ; RV64I-NEXT:    lui a2, 349525
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    addiw a1, a2, 1365
@@ -521,29 +518,30 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    addiw a1, a1, 257
 ; RV64I-NEXT:    call __muldi3
-; RV64I-NEXT:    slli s1, s1, 32
-; RV64I-NEXT:    srli s1, s1, 32
-; RV64I-NEXT:    beqz s1, .LBB8_2
+; RV64I-NEXT:    slli s0, s0, 32
+; RV64I-NEXT:    srli s0, s0, 32
+; RV64I-NEXT:    beqz s0, .LBB8_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    srliw s0, a0, 24
+; RV64I-NEXT:    srliw a0, a0, 24
+; RV64I-NEXT:    j .LBB8_3
 ; RV64I-NEXT:  .LBB8_2:
-; RV64I-NEXT:    mv a0, s0
-; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:  .LBB8_3:
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findFirstSet_i32:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    slli a1, a0, 32
-; RV64ZBB-NEXT:    srli a2, a1, 32
-; RV64ZBB-NEXT:    li a1, -1
-; RV64ZBB-NEXT:    beqz a2, .LBB8_2
+; RV64ZBB-NEXT:    srli a1, a1, 32
+; RV64ZBB-NEXT:    beqz a1, .LBB8_2
 ; RV64ZBB-NEXT:  # %bb.1:
-; RV64ZBB-NEXT:    ctzw a1, a0
+; RV64ZBB-NEXT:    ctzw a0, a0
+; RV64ZBB-NEXT:    ret
 ; RV64ZBB-NEXT:  .LBB8_2:
-; RV64ZBB-NEXT:    mv a0, a1
+; RV64ZBB-NEXT:    li a0, -1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
   %2 = icmp eq i32 %a, 0

llvm/test/CodeGen/RISCV/aext-to-sext.ll

@@ -78,12 +78,14 @@ bar:
 define i64 @sext_phi_constants(i32 signext %c) {
 ; RV64I-LABEL: sext_phi_constants:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    bnez a0, .LBB2_2
-; RV64I-NEXT:  # %bb.1: # %iffalse
-; RV64I-NEXT:    li a1, -2
-; RV64I-NEXT:  .LBB2_2: # %merge
-; RV64I-NEXT:    slli a0, a1, 32
+; RV64I-NEXT:    beqz a0, .LBB2_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    j .LBB2_3
+; RV64I-NEXT:  .LBB2_2: # %iffalse
+; RV64I-NEXT:    li a0, -2
+; RV64I-NEXT:  .LBB2_3: # %merge
+; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
   %a = icmp ne i32 %c, 0