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[CodeGen] Add generic INIT_UNDEF pseudo #106744

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Merged
merged 2 commits into from
Sep 5, 2024
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[CodeGen] Add generic INIT_UNDEF pseudo #106744

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[CodeGen] Add generic INIT_UNDEF pseudo
nikic Aug 30, 2024
1c3f59a
update tablegen test
nikic Sep 2, 2024
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9 changes: 0 additions & 9 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Expand Up @@ -2278,15 +2278,6 @@ class TargetInstrInfo : public MCInstrInfo {
llvm_unreachable("unknown number of operands necessary");
}

/// Gets the opcode for the Pseudo Instruction used to initialize
/// the undef value. If no Instruction is available, this will
/// fail compilation.
virtual unsigned getUndefInitOpcode(unsigned RegClassID) const {
(void)RegClassID;

llvm_unreachable("Unexpected register class.");
}

private:
mutable std::unique_ptr<MIRFormatter> Formatter;
unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
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5 changes: 5 additions & 0 deletions llvm/include/llvm/Support/TargetOpcodes.def
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Expand Up @@ -56,6 +56,11 @@ HANDLE_TARGET_OPCODE(INSERT_SUBREG)
/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
HANDLE_TARGET_OPCODE(IMPLICIT_DEF)

/// Explicit undef initialization used past IMPLICIT_DEF elimination in cases
/// where an undef operand must be allocated to a different register than an
/// early-clobber result operand.
HANDLE_TARGET_OPCODE(INIT_UNDEF)

/// SUBREG_TO_REG - Assert the value of bits in a super register.
/// The result of this instruction is the value of the second operand inserted
/// into the subregister specified by the third operand. All other bits are
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7 changes: 7 additions & 0 deletions llvm/include/llvm/Target/Target.td
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Expand Up @@ -1254,6 +1254,13 @@ def IMPLICIT_DEF : StandardPseudoInstruction {
let isAsCheapAsAMove = true;
let isMeta = true;
}
def INIT_UNDEF : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins);
let AsmString = "";
let hasSideEffects = false;
let Size = 0;
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I initially also added isMeta = true here like IMPLICIT_DEF does, but this caused more (positive looking) changes in riscv, so I left it out again.

Disclaimer: I don't really know what I'm doing here... or what exactly the effect of isMeta is.

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I'm also wondering whether we could directly reuse IMPLICIT_DEF, as it's basically the same thing. We normally remove IMPLICIT_DEF and replace it with undef flags, but it would probably be fine to reintroduce it afterwards?

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For the record, I tried reusing IMPLICIT_DEF but based on the resulting RISCV test diffs at least that doesn't work (I saw some vrgather.vi with equal registers with that change).

}
def SUBREG_TO_REG : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
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4 changes: 4 additions & 0 deletions llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
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Expand Up @@ -1832,6 +1832,10 @@ void AsmPrinter::emitFunctionBody() {
// This instruction is only used to note jump table debug info, it's
// purely meta information.
break;
case TargetOpcode::INIT_UNDEF:
// This is only used to influence register allocation behavior, no
// actual initialization is needed.
break;
default:
emitInstruction(&MI);
if (CanDoExtraAnalysis) {
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7 changes: 3 additions & 4 deletions llvm/lib/CodeGen/InitUndef.cpp
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Expand Up @@ -177,8 +177,7 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n");
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
TII->get(TII->getUndefInitOpcode(SubRegClass->getID())),
TmpInitSubReg);
TII->get(TargetOpcode::INIT_UNDEF), TmpInitSubReg);
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
TII->get(TargetOpcode::INSERT_SUBREG), NewReg)
Expand All @@ -203,9 +202,9 @@ bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
const TargetRegisterClass *TargetRegClass =
TRI->getLargestSuperClass(MRI->getRegClass(MO.getReg()));
LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n");
unsigned Opcode = TII->getUndefInitOpcode(TargetRegClass->getID());
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(Opcode), NewReg);
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII->get(TargetOpcode::INIT_UNDEF), NewReg);
MO.setReg(NewReg);
if (MO.isUndef())
MO.setIsUndef(false);
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6 changes: 0 additions & 6 deletions llvm/lib/Target/ARM/ARMAsmPrinter.cpp
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Expand Up @@ -2411,12 +2411,6 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
case ARM::SEH_EpilogEnd:
ATS.emitARMWinCFIEpilogEnd();
return;

case ARM::PseudoARMInitUndefMQPR:
case ARM::PseudoARMInitUndefSPR:
case ARM::PseudoARMInitUndefDPR_VFP2:
case ARM::PseudoARMInitUndefGPR:
return;
}

MCInst TmpInst;
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13 changes: 0 additions & 13 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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Expand Up @@ -546,19 +546,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {

std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
Register Reg) const override;

unsigned getUndefInitOpcode(unsigned RegClassID) const override {
if (RegClassID == ARM::MQPRRegClass.getID())
return ARM::PseudoARMInitUndefMQPR;
if (RegClassID == ARM::SPRRegClass.getID())
return ARM::PseudoARMInitUndefSPR;
if (RegClassID == ARM::DPR_VFP2RegClass.getID())
return ARM::PseudoARMInitUndefDPR_VFP2;
if (RegClassID == ARM::GPRRegClass.getID())
return ARM::PseudoARMInitUndefGPR;

llvm_unreachable("Unexpected register class.");
}
};

/// Get the operands corresponding to the given \p Pred value. By default, the
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12 changes: 0 additions & 12 deletions llvm/lib/Target/ARM/ARMInstrInfo.td
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Expand Up @@ -6549,15 +6549,3 @@ let isPseudo = 1 in {
let isTerminator = 1 in
def SEH_EpilogEnd : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
}


//===----------------------------------------------------------------------===//
// Pseudo Instructions for use when early-clobber is defined and Greedy Register
// Allocation is used. This ensures the constraint is used properly.
//===----------------------------------------------------------------------===//
let isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
def PseudoARMInitUndefMQPR : PseudoInst<(outs MQPR:$vd), (ins), NoItinerary, []>;
def PseudoARMInitUndefSPR : PseudoInst<(outs SPR:$sd), (ins), NoItinerary, []>;
def PseudoARMInitUndefDPR_VFP2 : PseudoInst<(outs DPR_VFP2:$dd), (ins), NoItinerary, []>;
def PseudoARMInitUndefGPR : PseudoInst<(outs GPR:$rd), (ins), NoItinerary, []>;
}
5 changes: 0 additions & 5 deletions llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
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Expand Up @@ -303,11 +303,6 @@ void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
case RISCV::KCFI_CHECK:
LowerKCFI_CHECK(*MI);
return;
case RISCV::PseudoRVVInitUndefM1:
case RISCV::PseudoRVVInitUndefM2:
case RISCV::PseudoRVVInitUndefM4:
case RISCV::PseudoRVVInitUndefM8:
return;
case TargetOpcode::STACKMAP:
return LowerSTACKMAP(*OutStreamer, SM, *MI);
case TargetOpcode::PATCHPOINT:
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15 changes: 0 additions & 15 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Expand Up @@ -293,21 +293,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {

unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;

unsigned getUndefInitOpcode(unsigned RegClassID) const override {
switch (RegClassID) {
case RISCV::VRRegClassID:
return RISCV::PseudoRVVInitUndefM1;
case RISCV::VRM2RegClassID:
return RISCV::PseudoRVVInitUndefM2;
case RISCV::VRM4RegClassID:
return RISCV::PseudoRVVInitUndefM4;
case RISCV::VRM8RegClassID:
return RISCV::PseudoRVVInitUndefM8;
default:
llvm_unreachable("Unexpected register class.");
}
}

protected:
const RISCVSubtarget &STI;

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9 changes: 0 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -6116,15 +6116,6 @@ foreach lmul = MxList in {
}
}

/// Empty pseudo for RISCVInitUndefPass
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 0,
isCodeGenOnly = 1 in {
def PseudoRVVInitUndefM1 : Pseudo<(outs VR:$vd), (ins), [], "">;
def PseudoRVVInitUndefM2 : Pseudo<(outs VRM2:$vd), (ins), [], "">;
def PseudoRVVInitUndefM4 : Pseudo<(outs VRM4:$vd), (ins), [], "">;
def PseudoRVVInitUndefM8 : Pseudo<(outs VRM8:$vd), (ins), [], "">;
}

//===----------------------------------------------------------------------===//
// 6. Configuration-Setting Instructions
//===----------------------------------------------------------------------===//
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir
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Expand Up @@ -9,8 +9,8 @@ body: |
; MIR-LABEL: name: vrgather_all_undef
; MIR: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; MIR-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
; MIR-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
; MIR-NEXT: [[INIT_UNDEF:%[0-9]+]]:vr = INIT_UNDEF
; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[INIT_UNDEF]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
; MIR-NEXT: $v8 = COPY %1
; MIR-NEXT: PseudoRET implicit $v8
%2:vr = IMPLICIT_DEF
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