Skip to content

[CodeGen] Use MachineInstr::all_defs (NFC) #106017

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Aug 26, 2024
Merged

[CodeGen] Use MachineInstr::all_defs (NFC) #106017

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions llvm/include/llvm/CodeGen/LiveVariables.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -253,8 +253,8 @@ class LiveVariables {
return false;

bool Removed = false;
for (MachineOperand &MO : MI.operands()) {
if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
for (MachineOperand &MO : MI.all_defs()) {
if (MO.getReg() == Reg) {
MO.setIsDead(false);
Removed = true;
break;
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -402,8 +402,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(

// Scan the register defs for this instruction and update
// live-ranges.
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef()) continue;
for (const MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg == 0) continue;
// Ignore KILLs and passthru registers for liveness...
Expand Down
21 changes: 8 additions & 13 deletions llvm/lib/CodeGen/MachineInstr.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2125,19 +2125,15 @@ bool MachineInstr::addRegisterDead(Register Reg,
}

void MachineInstr::clearRegisterDeads(Register Reg) {
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
continue;
MO.setIsDead(false);
}
for (MachineOperand &MO : all_defs())
if (MO.getReg() == Reg)
MO.setIsDead(false);
}

void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
continue;
MO.setIsUndef(IsUndef);
}
for (MachineOperand &MO : all_defs())
if (MO.getReg() == Reg && MO.getSubReg() != 0)
MO.setIsUndef(IsUndef);
}

void MachineInstr::addRegisterDefined(Register Reg,
Expand All @@ -2147,9 +2143,8 @@ void MachineInstr::addRegisterDefined(Register Reg,
if (MO)
return;
} else {
for (const MachineOperand &MO : operands()) {
if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
MO.getSubReg() == 0)
for (const MachineOperand &MO : all_defs()) {
if (MO.getReg() == Reg && MO.getSubReg() == 0)
return;
}
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/ModuloSchedule.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2667,8 +2667,8 @@ void ModuloScheduleExpanderMVE::calcNumUnroll() {
void ModuloScheduleExpanderMVE::updateInstrDef(MachineInstr *NewMI,
ValueMapTy &VRMap,
bool LastDef) {
for (MachineOperand &MO : NewMI->operands()) {
if (!MO.isReg() || !MO.getReg().isVirtual() || !MO.isDef())
for (MachineOperand &MO : NewMI->all_defs()) {
if (!MO.getReg().isVirtual())
continue;
Register Reg = MO.getReg();
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
Expand Down
14 changes: 4 additions & 10 deletions llvm/lib/CodeGen/RegAllocFast.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1329,9 +1329,8 @@ void RegAllocFastImpl::findAndSortDefOperandIndexes(const MachineInstr &MI) {
// we assign these.
SmallVector<unsigned> RegClassDefCounts(TRI->getNumRegClasses(), 0);

for (const MachineOperand &MO : MI.operands())
if (MO.isReg() && MO.isDef())
addRegClassDefCounts(RegClassDefCounts, MO.getReg());
for (const MachineOperand &MO : MI.all_defs())
addRegClassDefCounts(RegClassDefCounts, MO.getReg());

llvm::sort(DefOperandIndexes, [&](unsigned I0, unsigned I1) {
const MachineOperand &MO0 = MI.getOperand(I0);
Expand Down Expand Up @@ -1481,9 +1480,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
// Assign virtual register defs.
while (ReArrangedImplicitOps) {
ReArrangedImplicitOps = false;
for (MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
for (MachineOperand &MO : MI.all_defs()) {
Register Reg = MO.getReg();
if (Reg.isVirtual()) {
ReArrangedImplicitOps =
Expand All @@ -1499,10 +1496,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
// Free registers occupied by defs.
// Iterate operands in reverse order, so we see the implicit super register
// defs first (we added them earlier in case of <def,read-undef>).
for (MachineOperand &MO : reverse(MI.operands())) {
if (!MO.isReg() || !MO.isDef())
continue;

for (MachineOperand &MO : reverse(MI.all_defs())) {
Register Reg = MO.getReg();

// subreg defs don't free the full register. We left the subreg number
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/RegisterCoalescer.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3230,8 +3230,8 @@ void JoinVals::pruneValues(JoinVals &Other,
// Also remove dead flags since the joined live range will
// continue past this instruction.
for (MachineOperand &MO :
Indexes->getInstructionFromIndex(Def)->operands()) {
if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
Indexes->getInstructionFromIndex(Def)->all_defs()) {
if (MO.getReg() == Reg) {
if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef)
MO.setIsUndef(false);
MO.setIsDead(false);
Expand Down
Loading