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[X86] X86FixupVectorConstantsPass - add support for VMOVD/VMOVQ/VMOVSS/VMOVSD zero upper constant loads #73783
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@llvm/issue-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon)
X86FixupVectorConstantsPass currently just handles folding full vector loads to broadcasts, but we're missing the opportunity to use scalar loads for cases where all the upper vector elements are known to be zero.
We should be able to do this for SSE cases as well. Related to #71078 |
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This helps ensure the encoding details are next to the EVEX tag Noticed while preparing to add more constant commenting as part of llvm#73783 and llvm#71078
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…d/movq 'zero upper' instructions (#79000) If we're loading a vector constant that is known to be zero in the upper elements, then attempt to shrink the constant and just scalar load the lower 32/64 bits. Always chose the vzload/broadcast with the smallest constant load, and prefer vzload over broadcasts for same bitwidth to avoid domain flips (mainly a AVX1 issue). Fixes #73783
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X86FixupVectorConstantsPass currently just handles folding full vector loads to broadcasts, but we're missing the opportunity to use scalar loads for cases where all the upper vector elements are known to be zero.
We should be able to do this for SSE cases as well.
Related to #71078
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