Skip to content

[X86] X86FixupVectorConstantsPass - add support for VMOVD/VMOVQ/VMOVSS/VMOVSD zero upper constant loads #73783

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
RKSimon opened this issue Nov 29, 2023 · 1 comment · Fixed by #79000

Comments

@RKSimon
Copy link
Collaborator

RKSimon commented Nov 29, 2023

X86FixupVectorConstantsPass currently just handles folding full vector loads to broadcasts, but we're missing the opportunity to use scalar loads for cases where all the upper vector elements are known to be zero.

We should be able to do this for SSE cases as well.

Related to #71078

@llvmbot
Copy link
Member

llvmbot commented Nov 29, 2023

@llvm/issue-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

X86FixupVectorConstantsPass currently just handles folding full vector loads to broadcasts, but we're missing the opportunity to use scalar loads for cases where all the upper vector elements are known to be zero.

We should be able to do this for SSE cases as well.

Related to #71078

RKSimon added a commit to RKSimon/llvm-project that referenced this issue Jan 18, 2024
This helps ensure the encoding details are next to the EVEX tag

Noticed while preparing to add more constant commenting as part of llvm#73783 and llvm#71078
RKSimon added a commit that referenced this issue Jan 18, 2024
…78585)

This helps ensure the encoding details are next to the EVEX tag

Noticed while preparing to add more constant commenting as part of #73783 and #71078
RKSimon added a commit that referenced this issue Jan 22, 2024
…or future patches. NFC.

Add helper to convert raw APInt bit stream into ConstantDataVector elements.

This was used internally by rebuildSplatableConstant but will be reused in future patches for #73783 and #71078
RKSimon added a commit that referenced this issue Jan 24, 2024
…d/movq 'zero upper' instructions (#79000)

If we're loading a vector constant that is known to be zero in the upper elements, then attempt to shrink the constant and just scalar load the lower 32/64 bits.

Always chose the vzload/broadcast with the smallest constant load, and prefer vzload over broadcasts for same bitwidth to avoid domain flips (mainly a AVX1 issue).

Fixes #73783
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
2 participants