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AArch64: SVE: LLVM ERROR: Error while trying to spill X22 from class GPR64: Cannot scavenge register without an emergency spill slot! #55041

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rscottmanley opened this issue Apr 22, 2022 · 4 comments
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backend:AArch64 llvm:crash SVE ARM Scalable Vector Extensions

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@rscottmanley
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rscottmanley commented Apr 22, 2022

llc is getting abort in the Register Scavenger when using -aarch64-sve-vector-bits-min=256 and the -mcpu=neoverse-v1 target. It seems to be okay on a64fx and -aarch64-sve-vector-bits-min=512.

bugpoint reduced testcase here: https://godbolt.org/z/Er19PW8M1

cc @mcinally @paulwalker-arm

@fhahn fhahn added backend:AArch64 SVE ARM Scalable Vector Extensions llvm:crash and removed new issue labels Apr 22, 2022
@llvmbot
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llvmbot commented Apr 22, 2022

@llvm/issue-subscribers-backend-aarch64

@rscottmanley
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Also fine without -aarch64-sve-vector-bits-min=256

@peterwaller-arm
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Bisects to 86972f1 -- ping @brads55

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brads55 commented Apr 26, 2022

Review to fix this issue at https://reviews.llvm.org/D124457

@brads55 brads55 closed this as completed in 96bbd35 May 3, 2022
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Labels
backend:AArch64 llvm:crash SVE ARM Scalable Vector Extensions
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