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[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
Add support for generating TargetFrameIndex in complex patterns for indexed addressing modes in SVE. Additionally, add missing load/stores to getMemOpInfo and getLoadStoreImmIdx. Differential Revision: https://reviews.llvm.org/D112617
1 parent 014c6b0 commit 86972f1

14 files changed

+3428
-2922
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5050,6 +5050,14 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
50505050
SDValue &Base,
50515051
SDValue &OffImm) {
50525052
const EVT MemVT = getMemVTFromNode(*(CurDAG->getContext()), Root);
5053+
const DataLayout &DL = CurDAG->getDataLayout();
5054+
5055+
if (N.getOpcode() == ISD::FrameIndex) {
5056+
int FI = cast<FrameIndexSDNode>(N)->getIndex();
5057+
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
5058+
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64);
5059+
return true;
5060+
}
50535061

50545062
if (MemVT == EVT())
50555063
return false;
@@ -5073,6 +5081,11 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
50735081
return false;
50745082

50755083
Base = N.getOperand(0);
5084+
if (Base.getOpcode() == ISD::FrameIndex) {
5085+
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
5086+
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
5087+
}
5088+
50765089
OffImm = CurDAG->getTargetConstant(Offset, SDLoc(N), MVT::i64);
50775090
return true;
50785091
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 69 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2263,32 +2263,35 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
22632263
case AArch64::STNPSi:
22642264
case AArch64::LDG:
22652265
case AArch64::STGPi:
2266+
22662267
case AArch64::LD1B_IMM:
2267-
case AArch64::LD1H_IMM:
2268-
case AArch64::LD1W_IMM:
2269-
case AArch64::LD1D_IMM:
2270-
case AArch64::ST1B_IMM:
2271-
case AArch64::ST1H_IMM:
2272-
case AArch64::ST1W_IMM:
2273-
case AArch64::ST1D_IMM:
22742268
case AArch64::LD1B_H_IMM:
2269+
case AArch64::LD1B_S_IMM:
2270+
case AArch64::LD1B_D_IMM:
22752271
case AArch64::LD1SB_H_IMM:
2272+
case AArch64::LD1SB_S_IMM:
2273+
case AArch64::LD1SB_D_IMM:
2274+
case AArch64::LD1H_IMM:
22762275
case AArch64::LD1H_S_IMM:
2276+
case AArch64::LD1H_D_IMM:
22772277
case AArch64::LD1SH_S_IMM:
2278+
case AArch64::LD1SH_D_IMM:
2279+
case AArch64::LD1W_IMM:
22782280
case AArch64::LD1W_D_IMM:
22792281
case AArch64::LD1SW_D_IMM:
2282+
case AArch64::LD1D_IMM:
2283+
2284+
case AArch64::ST1B_IMM:
22802285
case AArch64::ST1B_H_IMM:
2281-
case AArch64::ST1H_S_IMM:
2282-
case AArch64::ST1W_D_IMM:
2283-
case AArch64::LD1B_S_IMM:
2284-
case AArch64::LD1SB_S_IMM:
2285-
case AArch64::LD1H_D_IMM:
2286-
case AArch64::LD1SH_D_IMM:
22872286
case AArch64::ST1B_S_IMM:
2288-
case AArch64::ST1H_D_IMM:
2289-
case AArch64::LD1B_D_IMM:
2290-
case AArch64::LD1SB_D_IMM:
22912287
case AArch64::ST1B_D_IMM:
2288+
case AArch64::ST1H_IMM:
2289+
case AArch64::ST1H_S_IMM:
2290+
case AArch64::ST1H_D_IMM:
2291+
case AArch64::ST1W_IMM:
2292+
case AArch64::ST1W_D_IMM:
2293+
case AArch64::ST1D_IMM:
2294+
22922295
case AArch64::LD1RB_IMM:
22932296
case AArch64::LD1RB_H_IMM:
22942297
case AArch64::LD1RB_S_IMM:
@@ -2305,6 +2308,32 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
23052308
case AArch64::LD1RW_D_IMM:
23062309
case AArch64::LD1RSW_IMM:
23072310
case AArch64::LD1RD_IMM:
2311+
2312+
case AArch64::LDNT1B_ZRI:
2313+
case AArch64::LDNT1H_ZRI:
2314+
case AArch64::LDNT1W_ZRI:
2315+
case AArch64::LDNT1D_ZRI:
2316+
case AArch64::STNT1B_ZRI:
2317+
case AArch64::STNT1H_ZRI:
2318+
case AArch64::STNT1W_ZRI:
2319+
case AArch64::STNT1D_ZRI:
2320+
2321+
case AArch64::LDNF1B_IMM:
2322+
case AArch64::LDNF1B_H_IMM:
2323+
case AArch64::LDNF1B_S_IMM:
2324+
case AArch64::LDNF1B_D_IMM:
2325+
case AArch64::LDNF1SB_H_IMM:
2326+
case AArch64::LDNF1SB_S_IMM:
2327+
case AArch64::LDNF1SB_D_IMM:
2328+
case AArch64::LDNF1H_IMM:
2329+
case AArch64::LDNF1H_S_IMM:
2330+
case AArch64::LDNF1H_D_IMM:
2331+
case AArch64::LDNF1SH_S_IMM:
2332+
case AArch64::LDNF1SH_D_IMM:
2333+
case AArch64::LDNF1W_IMM:
2334+
case AArch64::LDNF1W_D_IMM:
2335+
case AArch64::LDNF1SW_D_IMM:
2336+
case AArch64::LDNF1D_IMM:
23082337
return 3;
23092338
case AArch64::ADDG:
23102339
case AArch64::STGOffset:
@@ -2855,10 +2884,22 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
28552884
case AArch64::LD1H_IMM:
28562885
case AArch64::LD1W_IMM:
28572886
case AArch64::LD1D_IMM:
2887+
case AArch64::LDNT1B_ZRI:
2888+
case AArch64::LDNT1H_ZRI:
2889+
case AArch64::LDNT1W_ZRI:
2890+
case AArch64::LDNT1D_ZRI:
28582891
case AArch64::ST1B_IMM:
28592892
case AArch64::ST1H_IMM:
28602893
case AArch64::ST1W_IMM:
28612894
case AArch64::ST1D_IMM:
2895+
case AArch64::STNT1B_ZRI:
2896+
case AArch64::STNT1H_ZRI:
2897+
case AArch64::STNT1W_ZRI:
2898+
case AArch64::STNT1D_ZRI:
2899+
case AArch64::LDNF1B_IMM:
2900+
case AArch64::LDNF1H_IMM:
2901+
case AArch64::LDNF1W_IMM:
2902+
case AArch64::LDNF1D_IMM:
28622903
// A full vectors worth of data
28632904
// Width = mbytes * elements
28642905
Scale = TypeSize::Scalable(16);
@@ -2875,6 +2916,12 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
28752916
case AArch64::ST1B_H_IMM:
28762917
case AArch64::ST1H_S_IMM:
28772918
case AArch64::ST1W_D_IMM:
2919+
case AArch64::LDNF1B_H_IMM:
2920+
case AArch64::LDNF1SB_H_IMM:
2921+
case AArch64::LDNF1H_S_IMM:
2922+
case AArch64::LDNF1SH_S_IMM:
2923+
case AArch64::LDNF1W_D_IMM:
2924+
case AArch64::LDNF1SW_D_IMM:
28782925
// A half vector worth of data
28792926
// Width = mbytes * elements
28802927
Scale = TypeSize::Scalable(8);
@@ -2888,6 +2935,10 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
28882935
case AArch64::LD1SH_D_IMM:
28892936
case AArch64::ST1B_S_IMM:
28902937
case AArch64::ST1H_D_IMM:
2938+
case AArch64::LDNF1B_S_IMM:
2939+
case AArch64::LDNF1SB_S_IMM:
2940+
case AArch64::LDNF1H_D_IMM:
2941+
case AArch64::LDNF1SH_D_IMM:
28912942
// A quarter vector worth of data
28922943
// Width = mbytes * elements
28932944
Scale = TypeSize::Scalable(4);
@@ -2898,6 +2949,8 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
28982949
case AArch64::LD1B_D_IMM:
28992950
case AArch64::LD1SB_D_IMM:
29002951
case AArch64::ST1B_D_IMM:
2952+
case AArch64::LDNF1B_D_IMM:
2953+
case AArch64::LDNF1SB_D_IMM:
29012954
// A eighth vector worth of data
29022955
// Width = mbytes * elements
29032956
Scale = TypeSize::Scalable(2);

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2200,10 +2200,6 @@ let Predicates = [HasSVEorStreamingSVE] in {
22002200
def _imm : Pat<(Store (Ty ZPR:$val), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)),
22012201
(RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
22022202
}
2203-
let AddedComplexity = 3 in {
2204-
def _fi : Pat<(Store (Ty ZPR:$val), (am_sve_fi GPR64sp:$base, simm4s1:$offset)),
2205-
(RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
2206-
}
22072203

22082204
def : Pat<(Store (Ty ZPR:$val), GPR64:$base),
22092205
(RegImmInst ZPR:$val, (PTrue 31), GPR64:$base, (i64 0))>;
@@ -2240,10 +2236,6 @@ let Predicates = [HasSVEorStreamingSVE] in {
22402236
def _imm: Pat<(Ty (Load (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset))),
22412237
(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
22422238
}
2243-
let AddedComplexity = 3 in {
2244-
def _fi : Pat<(Ty (Load (am_sve_fi GPR64sp:$base, simm4s1:$offset))),
2245-
(RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
2246-
}
22472239

22482240
def : Pat<(Ty (Load GPR64:$base)),
22492241
(RegImmInst (PTrue 31), GPR64:$base, (i64 0))>;

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