[X86] SLM has incorrect scheduling information for PMULLD

[topperc]

Bugzilla Link	37059
Version	trunk
OS	Windows NT
Blocks	#31672
CC	@RKSimon,@phoebewang

Extended Description

I had tried to fix this in r328914, but got perf regressions in some benchmarks in Intel's internal list. So I reverted it back to old behavior in r329593.

Looking at the benchmarks, they regressed in 32-bit mode and it looks like register pressure may have increased leading to additional spills. But I thought 32-bit mode scheduling favored register pressure so I'm not sure what's going on.

[RKSimon]

Have you been able to get llvm-exegesis running on silvermont yet?

I'm curious how accurate the model is in general and whether that is the root cause of the issue - increasing PMULLD costs so much may just lead such problems to be more obvious.

[RKSimon]

Craig - do you have any suggestions on how I can replicate this on publicly available benchmarks?

I've been cleaning up the SLM model using llvm-exegesis on a Z8350 box but haven't been able to replicate this; this is building for -m32 on 64-bit ubuntu.

It might be that the more aggressive folds we now have to PMADDWD/PMULLW+PMULHW have fixed/hidden it.

Otherwise I'm tempted to just fix the model and see if anyone reports a regression that we can then address more directly, possibly via regalloc/TwoAddressInstructionPass.