[X86] SandyBridge/Haswell/Broadwell/Skylake scheduler models lose the ReadAdvance information for all instructions that load from memory and read another operand from a register

[topperc]

Bugzilla Link	36951
Resolution	FIXED
Resolved on	Oct 04, 2018 09:39
Version	trunk
OS	Windows NT
Blocks	#31672
CC	@adibiagio,@RKSimon

Extended Description

For example

[0,0] DeER . . addl %edi, %esi
[0,1] D=eeeeeeER addl (%rdi), %esi

The second instruction shouldn't have to wait on the first instruction to writeback before it can execute.

[RKSimon]

Works in trunk - added test case at rL343795