[X86][SSE] Split gpr/vector WriteMove, WriteLoad, WriteStore scheduler classes

[RKSimon]

Bugzilla Link	36726
Resolution	FIXED
Resolved on	May 27, 2018 04:36
Version	trunk
OS	Windows NT
Blocks	#31672 #36479
Fixed by commit(s)	327630

Extended Description

We currently use WriteMove, WriteLoad, WriteStore for x86 gpr, vector and mask registers.

These need to be split to better account for differences in behaviour without requiring full overloading of the scheduling of individual instructions.

[llvmbot]

Does it mean you'd like to get something like WriteMove, VWriteMove and MWriteMove?

[RKSimon]

Does it mean you'd like to get something like WriteMove, VWriteMove and
MWriteMove?

Yes, I've started this at https://reviews.llvm.org/D44471 - still not sure if we need a WriteMaskMove etc or whether they can share WriteVecMove.

The concern I have is what to do for moves from one register file to another, which are all WriteMove at the moment.

[llvmbot]

I suppose you could use WriteR1R2Move for specific intrs. BTW, could you list some of interesting instrs?

[RKSimon]

Basic SSE/AVX support was added at rL327630

[RKSimon]

I suppose you could use WriteR1R2Move for specific intrs. BTW, could you
list some of interesting instrs?

I'd say hold off on this for now, once Andrea has added multiple PRF support to llvm-mca and the schedulers we can look again at what to do to scheduler reg2reg transfers.

[RKSimon]

Resolving, Float/Integer vector move/load/stores were split off by rL327630.

Andrea's work on variants [D47374 and beyond] will allow move-idioms to be correctly modelled.

[RKSimon]

mentioned in issue #36479