Closed
Description
| Bugzilla Link | 35713 |
| Resolution | FIXED |
| Resolved on | Jun 28, 2018 07:39 |
| Version | trunk |
| OS | All |
| Blocks | #31672 |
| CC | @RKSimon |
| Fixed by commit(s) | 334407 |
Extended Description
I would be very surprised if VPERMW is on port0. Seems more likely on port5 like every other shuffle. The memory form is using port23 and port5 in the scheduler model.
def SKXWriteResGroup72 : SchedWriteRes<[SKXPort0]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
...
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup72], (instregex "VPERMWZrr(b?)(k?)(z?)")>;