[X86] VPGATHER instructions missing from broadwell scheduler model

[topperc]

Bugzilla Link	35676
Resolution	FIXED
Resolved on	Feb 03, 2020 18:08
Version	trunk
OS	All
Blocks	#31672
CC	@adibiagio,@RKSimon,@rotateright
Fixed by commit(s)	c7768ce

Extended Description

Broadwell is missing all the integer gather instructions. Only the FP ones are present.

[RKSimon]

Duplicating the PS/PD equivalent versions for D/Q is trivial, my only question is whether these schedule models are ever going to regenerated again? In which case, what is being done to make sure Intel's internal scripts are updated?

[topperc]

If you look at the models the PS/PD don't always match the D/Q. Which seems surprising to me.

[RKSimon]

If you look at the models the PS/PD don't always match the D/Q. Which seems
surprising to me.

Very surprising. Agner says Broadwell does match at least, what says otherwise?

[topperc]

From Haswell for example

def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> {
let Latency = 26;
let NumMicroOps = 12;
let ResourceCycles = [2,2,1,3,2,2];
}
def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm,
VPGATHERDQrm,
VPGATHERDDrm)>;

def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
let Latency = 25;
let NumMicroOps = 22;
let ResourceCycles = [5,3,4,1,5,4];
}
def: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>;

def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
let Latency = 25;
let NumMicroOps = 15;
let ResourceCycles = [3,3,2,1,4,2];
}
def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm,
VGATHERDPSrm)>;

[RKSimon]

I think https://reviews.llvm.org/D73844 will cover this?

[topperc]

Fixed by c7768ce