Description
Bugzilla Link | 17367 |
Version | trunk |
OS | All |
Depends On | #34991 |
Blocks | #31672 |
CC | @adibiagio,@topperc,@hfinkel,@jryans,@LebedevRI,@RKSimon,@rotateright,@ZviRackover |
Extended Description
Each instruction in X86InstrSSE.td needs a SchedRW list.
This is a list of types defined in X86Schedule.td.
If new types are added (e.g. WritePopCnt), then a SB/HWWriteRes entry should be added to X86SchedSandyBridge.td and X86SchedHaswell.td.
Once this is done we can mark the model complete. See this FIXME
def SandyBridgeModel...
// FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
// the scheduler to assign a default model to unrecognized opcodes.
let CompleteModel = 0;
Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too.
LLVM ERROR: DefIdx 0 exceeds machine model writes for ...