RISC-V: enable `-mno-strict-align` when `Zicclsm` is enabled

[newpavlov]

Otherwise LLVM generates terrible code for misaligned loads/stores, as can be seen here: https://rust.godbolt.org/z/ax1bqeeKx

The RISC-V Profiles specification states the following

Even though mandated, misaligned loads and stores might execute extremely slowly. Standard software distributions should assume their existence only for correctness, not for performance.

This footnote is not present in the RVA23 spec, but it's unclear whether it got deprecated or implicitly inherited from the profiles spec.

In practice, we probably can expect that most hardware which declares Zicclsm support will have "fast" misaligned support implemented in hardware.

As another data point, it looks like Linux also considers that enabled Zicclsm means "fast" misaligned operations. From this patch:

If Zicclsm is present, the kernel will set both scalar and vector unaligned access speed to FAST.

[dtcxzyw]

See #108551.

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Artyom Pavlov (newpavlov)

Otherwise LLVM generates terrible code for misaligned loads/stores, as can be seen here: https://rust.godbolt.org/z/ax1bqeeKx

The RISC-V Profiles specification states the following
>Even though mandated, misaligned loads and stores might execute extremely slowly. Standard software distributions should assume their existence only for correctness, not for performance.

This footnote is not present in the RVA23 spec, but it's unclear whether it got deprecated or implicitly inherited from the profiles spec.

In practice, we probably can expect that most hardware which declares Zicclsm support will have "fast" misaligned support implemented in hardware.

As another data point, it looks like Linux also considers that enabled Zicclsm means "fast" misaligned operations. From [this patch](https://lwn.net/ml/all/20240613191616.2101821-1-jesse@rivosinc.com/):
>If Zicclsm is present, the kernel will set both scalar and vector unaligned access speed to FAST.

[newpavlov]

@dtcxzyw
I explicitly discussed the spec footnote. Arguably, compilers should ignore it and denonce hardware which declares Zicclsm support, but relies on emulated misaligned operations. It looks like hardware which targets the RVA profiles overwhelmingly supports native misaligned operations. Otherwise, codegen for misaligned operations will be extremely terrible for everyone.

Either way, it would be nice to get an explicit clarification from the RISC-V folks.

[topperc]

I worry that many hardware vendors are going to want to claim to be RVA23 compliant, but rely on trap and emulate of unaligned accesses.

[topperc]

It looks like hardware which targets the RVA profiles overwhelmingly supports native misaligned operations.

Can you provide public documentation that demonstrates that this is "overwhelming"?

[newpavlov]

Citing this message:

As my own testing shows (see link below), the C906, C910, SpacemiT X60 all support fast misaligned accesses. The only common SoC that doesn't is the JH7110 (U74 core), and near future SiFive cores (P550, P670) are known to have hardware misaligned access handling.

IIUC JH7110 does not claim support of an RVA profile.

I worry that many hardware vendors are going to want to claim to be RVA23 compliant, but rely on trap and emulate of unaligned accesses.

Wouldn't this hypothetical hardware clash with how Linux interprets Zicclsm, thus making them non-compliant in practice?

[cyyself]

Wouldn't this hypothetical hardware clash with how Linux interprets Zicclsm, thus making them non-compliant in practice?

Actually, the scalar misaligned load/store has been handled by OpenSBI since v0.1 6 years ago.

[topperc]

-mno-strict-align includes misaligned vector which is known to crash on the Spacemit X60

[newpavlov]

@cyyself
I am no sure how it's relevant to the current discussion. IIUC Linux assumes that Zicclsm means "fast" misaligned operations, breaking this assumption would make such hardware "non-compliant" with how Linux interprets the spec.

[newpavlov]

@topperc
Spacemit X60 does not claim support of an RVA profile, no? Thus Zicclsm will not be enabled for it.

[topperc]

@topperc Spacemit X60 does not claim support of an RVA profile, no? Thus Zicclsm will not be enabled for it.

RVA23 isn't ratified so I'm not sure anyone would claim support for it yet.