[RISC-V] expandload should compile to viota+vrgather

[Validark]

export fn expandload16(a: *const [16]u8, b: u16, c: @Vector(16, u8)) @Vector(16, u8) {
    return struct {
        extern fn @"llvm.masked.expandload.v16i8"(@TypeOf(a), @Vector(16, u1), @TypeOf(c)) callconv(.Unspecified) @Vector(16, u8);
    }.@"llvm.masked.expandload.v16i8"(a, @as(@Vector(16, u1), @bitCast(b)), c);
}

define dso_local <16 x i8> @expandload16(ptr nocapture nonnull readonly align 1 %0, i16 zeroext %1, <16 x i8> %2) local_unnamed_addr {
Entry:
  %3 = bitcast i16 %1 to <16 x i1>
  %4 = tail call fastcc <16 x i8> @llvm.masked.expandload.v16i8(ptr nonnull readonly align 1 %0, <16 x i1> %3, <16 x i8> %2)
  ret <16 x i8> %4
}

declare void @llvm.dbg.value(metadata, metadata, metadata) #1

declare fastcc <16 x i8> @llvm.masked.expandload.v16i8(ptr nocapture, <16 x i1>, <16 x i8>) #2

When compiled for the Sifive x280, we check bit-by-bit and jump based on that:

...
...
...
.LBB0_2:
        andi    a2, a1, 4
        bnez    a2, .LBB0_20
.LBB0_3:
        andi    a2, a1, 8
        bnez    a2, .LBB0_21
.LBB0_4:
        andi    a2, a1, 16
        bnez    a2, .LBB0_22
.LBB0_5:
        andi    a2, a1, 32
        bnez    a2, .LBB0_23
.LBB0_6:
        andi    a2, a1, 64
        bnez    a2, .LBB0_24
.LBB0_7:
        andi    a2, a1, 128
        bnez    a2, .LBB0_25
.LBB0_8:
        andi    a2, a1, 256
        bnez    a2, .LBB0_26
.LBB0_9:
        andi    a2, a1, 512
        bnez    a2, .LBB0_27
.LBB0_10:
        andi    a2, a1, 1024
        bnez    a2, .LBB0_28
...
...
...

It should be able to work according to the documentation here:

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1651-synthesizing-vdecompress

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Niles Salter (Validark)

```zig export fn expandload16(a: *const [16]u8, b: u16, c: @Vector(16, u8)) @Vector(16, u8) { return struct { extern fn @"llvm.masked.expandload.v16i8"(@TypeOf(a), @Vector(16, u1), @TypeOf(c)) callconv(.Unspecified) @Vector(16, u8); }.@"llvm.masked.expandload.v16i8"(a, @as(@Vector(16, u1), @bitCast(b)), c); } ```

define dso_local &lt;16 x i8&gt; @<!-- -->expandload16(ptr nocapture nonnull readonly align 1 %0, i16 zeroext %1, &lt;16 x i8&gt; %2) local_unnamed_addr {
Entry:
  %3 = bitcast i16 %1 to &lt;16 x i1&gt;
  %4 = tail call fastcc &lt;16 x i8&gt; @<!-- -->llvm.masked.expandload.v16i8(ptr nonnull readonly align 1 %0, &lt;16 x i1&gt; %3, &lt;16 x i8&gt; %2)
  ret &lt;16 x i8&gt; %4
}

declare void @<!-- -->llvm.dbg.value(metadata, metadata, metadata) #<!-- -->1

declare fastcc &lt;16 x i8&gt; @<!-- -->llvm.masked.expandload.v16i8(ptr nocapture, &lt;16 x i1&gt;, &lt;16 x i8&gt;) #<!-- -->2

When compiled for the Sifive x280, we check bit-by-bit and jump based on that:

...
...
...
.LBB0_2:
        andi    a2, a1, 4
        bnez    a2, .LBB0_20
.LBB0_3:
        andi    a2, a1, 8
        bnez    a2, .LBB0_21
.LBB0_4:
        andi    a2, a1, 16
        bnez    a2, .LBB0_22
.LBB0_5:
        andi    a2, a1, 32
        bnez    a2, .LBB0_23
.LBB0_6:
        andi    a2, a1, 64
        bnez    a2, .LBB0_24
.LBB0_7:
        andi    a2, a1, 128
        bnez    a2, .LBB0_25
.LBB0_8:
        andi    a2, a1, 256
        bnez    a2, .LBB0_26
.LBB0_9:
        andi    a2, a1, 512
        bnez    a2, .LBB0_27
.LBB0_10:
        andi    a2, a1, 1024
        bnez    a2, .LBB0_28
...
...
...

It should be able to work according to the documentation here:

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1651-synthesizing-vdecompress