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[RISCV] Lower fixed-length bf16 vector bitcasts (#114938)
Currently we crash because we can't select it. Also add tests for f16 with zvfhmin.
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2 files changed

+152
-14
lines changed

2 files changed

+152
-14
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1448,6 +1448,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
14481448
Custom);
14491449
if (Subtarget.hasStdExtZfhminOrZhinxmin())
14501450
setOperationAction(ISD::BITCAST, MVT::f16, Custom);
1451+
if (Subtarget.hasStdExtZfbfmin())
1452+
setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
14511453
if (Subtarget.hasStdExtFOrZfinx())
14521454
setOperationAction(ISD::BITCAST, MVT::f32, Custom);
14531455
if (Subtarget.hasStdExtDOrZdinx())

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

Lines changed: 150 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,16 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh -verify-machineinstrs \
3-
; RUN: -target-abi=ilp32d < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh -verify-machineinstrs \
5-
; RUN: -target-abi=lp64d < %s | FileCheck %s --check-prefixes=CHECK,RV64
6-
; RUN: llc -mtriple=riscv32 -mattr=+zve32f,+zvl128b,+d,+zvfh \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh,+zfbfmin,+zvfbfmin -verify-machineinstrs \
3+
; RUN: -target-abi=ilp32d < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh,+zfbfmin,+zvfbfmin -verify-machineinstrs \
5+
; RUN: -target-abi=lp64d < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64
6+
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin -verify-machineinstrs \
7+
; RUN: -target-abi=ilp32d < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV32
8+
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin -verify-machineinstrs \
9+
; RUN: -target-abi=lp64d < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,RV64
10+
; RUN: llc -mtriple=riscv32 -mattr=+zve32f,+zvl128b,+d,+zvfh,+zfbfmin,+zvfbfmin \
711
; RUN: -verify-machineinstrs -target-abi=ilp32d < %s | FileCheck %s \
812
; RUN: --check-prefixes=ELEN32,RV32ELEN32
9-
; RUN: llc -mtriple=riscv64 -mattr=+zve32f,+zvl128b,+d,+zvfh \
13+
; RUN: llc -mtriple=riscv64 -mattr=+zve32f,+zvl128b,+d,+zvfh,+zfbfmin,+zvfbfmin \
1014
; RUN: -verify-machineinstrs -target-abi=lp64d < %s | FileCheck %s \
1115
; RUN: --check-prefixes=ELEN32,RV64ELEN32
1216

@@ -262,13 +266,92 @@ define i64 @bitcast_v1i64_i64(<1 x i64> %a) {
262266
ret i64 %b
263267
}
264268

265-
define half @bitcast_v2i8_f16(<2 x i8> %a) {
266-
; CHECK-LABEL: bitcast_v2i8_f16:
269+
define bfloat @bitcast_v2i8_bf16(<2 x i8> %a) {
270+
; CHECK-LABEL: bitcast_v2i8_bf16:
267271
; CHECK: # %bb.0:
268272
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
269-
; CHECK-NEXT: vfmv.f.s fa0, v8
273+
; CHECK-NEXT: vmv.x.s a0, v8
274+
; CHECK-NEXT: fmv.h.x fa0, a0
275+
; CHECK-NEXT: ret
276+
;
277+
; ELEN32-LABEL: bitcast_v2i8_bf16:
278+
; ELEN32: # %bb.0:
279+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
280+
; ELEN32-NEXT: vmv.x.s a0, v8
281+
; ELEN32-NEXT: fmv.h.x fa0, a0
282+
; ELEN32-NEXT: ret
283+
%b = bitcast <2 x i8> %a to bfloat
284+
ret bfloat %b
285+
}
286+
287+
define bfloat @bitcast_v1i16_bf16(<1 x i16> %a) {
288+
; CHECK-LABEL: bitcast_v1i16_bf16:
289+
; CHECK: # %bb.0:
290+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
291+
; CHECK-NEXT: vmv.x.s a0, v8
292+
; CHECK-NEXT: fmv.h.x fa0, a0
293+
; CHECK-NEXT: ret
294+
;
295+
; ELEN32-LABEL: bitcast_v1i16_bf16:
296+
; ELEN32: # %bb.0:
297+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
298+
; ELEN32-NEXT: vmv.x.s a0, v8
299+
; ELEN32-NEXT: fmv.h.x fa0, a0
300+
; ELEN32-NEXT: ret
301+
%b = bitcast <1 x i16> %a to bfloat
302+
ret bfloat %b
303+
}
304+
305+
define bfloat @bitcast_v1bf16_bf16(<1 x bfloat> %a) {
306+
; CHECK-LABEL: bitcast_v1bf16_bf16:
307+
; CHECK: # %bb.0:
308+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
309+
; CHECK-NEXT: vmv.x.s a0, v8
310+
; CHECK-NEXT: fmv.h.x fa0, a0
311+
; CHECK-NEXT: ret
312+
;
313+
; ELEN32-LABEL: bitcast_v1bf16_bf16:
314+
; ELEN32: # %bb.0:
315+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
316+
; ELEN32-NEXT: vmv.x.s a0, v8
317+
; ELEN32-NEXT: fmv.h.x fa0, a0
318+
; ELEN32-NEXT: ret
319+
%b = bitcast <1 x bfloat> %a to bfloat
320+
ret bfloat %b
321+
}
322+
323+
define <1 x bfloat> @bitcast_bf16_v1bf16(bfloat %a) {
324+
; CHECK-LABEL: bitcast_bf16_v1bf16:
325+
; CHECK: # %bb.0:
326+
; CHECK-NEXT: fmv.x.h a0, fa0
327+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
328+
; CHECK-NEXT: vmv.s.x v8, a0
270329
; CHECK-NEXT: ret
271330
;
331+
; ELEN32-LABEL: bitcast_bf16_v1bf16:
332+
; ELEN32: # %bb.0:
333+
; ELEN32-NEXT: fmv.x.h a0, fa0
334+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
335+
; ELEN32-NEXT: vmv.s.x v8, a0
336+
; ELEN32-NEXT: ret
337+
%b = bitcast bfloat %a to <1 x bfloat>
338+
ret <1 x bfloat> %b
339+
}
340+
341+
define half @bitcast_v2i8_f16(<2 x i8> %a) {
342+
; ZVFH-LABEL: bitcast_v2i8_f16:
343+
; ZVFH: # %bb.0:
344+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
345+
; ZVFH-NEXT: vfmv.f.s fa0, v8
346+
; ZVFH-NEXT: ret
347+
;
348+
; ZVFHMIN-LABEL: bitcast_v2i8_f16:
349+
; ZVFHMIN: # %bb.0:
350+
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
351+
; ZVFHMIN-NEXT: vmv.x.s a0, v8
352+
; ZVFHMIN-NEXT: fmv.h.x fa0, a0
353+
; ZVFHMIN-NEXT: ret
354+
;
272355
; ELEN32-LABEL: bitcast_v2i8_f16:
273356
; ELEN32: # %bb.0:
274357
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
@@ -279,11 +362,18 @@ define half @bitcast_v2i8_f16(<2 x i8> %a) {
279362
}
280363

281364
define half @bitcast_v1i16_f16(<1 x i16> %a) {
282-
; CHECK-LABEL: bitcast_v1i16_f16:
283-
; CHECK: # %bb.0:
284-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
285-
; CHECK-NEXT: vfmv.f.s fa0, v8
286-
; CHECK-NEXT: ret
365+
; ZVFH-LABEL: bitcast_v1i16_f16:
366+
; ZVFH: # %bb.0:
367+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
368+
; ZVFH-NEXT: vfmv.f.s fa0, v8
369+
; ZVFH-NEXT: ret
370+
;
371+
; ZVFHMIN-LABEL: bitcast_v1i16_f16:
372+
; ZVFHMIN: # %bb.0:
373+
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
374+
; ZVFHMIN-NEXT: vmv.x.s a0, v8
375+
; ZVFHMIN-NEXT: fmv.h.x fa0, a0
376+
; ZVFHMIN-NEXT: ret
287377
;
288378
; ELEN32-LABEL: bitcast_v1i16_f16:
289379
; ELEN32: # %bb.0:
@@ -294,6 +384,52 @@ define half @bitcast_v1i16_f16(<1 x i16> %a) {
294384
ret half %b
295385
}
296386

387+
define half @bitcast_v1f16_f16(<1 x half> %a) {
388+
; ZVFH-LABEL: bitcast_v1f16_f16:
389+
; ZVFH: # %bb.0:
390+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
391+
; ZVFH-NEXT: vfmv.f.s fa0, v8
392+
; ZVFH-NEXT: ret
393+
;
394+
; ZVFHMIN-LABEL: bitcast_v1f16_f16:
395+
; ZVFHMIN: # %bb.0:
396+
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
397+
; ZVFHMIN-NEXT: vmv.x.s a0, v8
398+
; ZVFHMIN-NEXT: fmv.h.x fa0, a0
399+
; ZVFHMIN-NEXT: ret
400+
;
401+
; ELEN32-LABEL: bitcast_v1f16_f16:
402+
; ELEN32: # %bb.0:
403+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
404+
; ELEN32-NEXT: vfmv.f.s fa0, v8
405+
; ELEN32-NEXT: ret
406+
%b = bitcast <1 x half> %a to half
407+
ret half %b
408+
}
409+
410+
define <1 x half> @bitcast_f16_v1f16(half %a) {
411+
; ZVFH-LABEL: bitcast_f16_v1f16:
412+
; ZVFH: # %bb.0:
413+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
414+
; ZVFH-NEXT: vfmv.s.f v8, fa0
415+
; ZVFH-NEXT: ret
416+
;
417+
; ZVFHMIN-LABEL: bitcast_f16_v1f16:
418+
; ZVFHMIN: # %bb.0:
419+
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
420+
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
421+
; ZVFHMIN-NEXT: vmv.s.x v8, a0
422+
; ZVFHMIN-NEXT: ret
423+
;
424+
; ELEN32-LABEL: bitcast_f16_v1f16:
425+
; ELEN32: # %bb.0:
426+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
427+
; ELEN32-NEXT: vfmv.s.f v8, fa0
428+
; ELEN32-NEXT: ret
429+
%b = bitcast half %a to <1 x half>
430+
ret <1 x half> %b
431+
}
432+
297433
define float @bitcast_v4i8_f32(<4 x i8> %a) {
298434
; CHECK-LABEL: bitcast_v4i8_f32:
299435
; CHECK: # %bb.0:

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