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davemgreendavemgreen
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[ARM] Correct Cortex-M55 scheduling info for VMINV/VMAXV
It appears that these were the wrong way around, with the wrong type sizes taking extra cycles. The smaller i8 sizes are now the ones marked as taking longer.
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lines changed

2 files changed

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lines changed

‎llvm/lib/Target/ARM/ARMScheduleM55.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -353,9 +353,9 @@ def : InstRW<[M55Write2IntE2], (instregex "MVE_VHADD")>;
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def : InstRW<[M55Write2IntE2], (instregex "MVE_VHCADD")>;
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def : InstRW<[M55Write2IntE2], (instregex "MVE_VHSUB")>;
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def : InstRW<[M55Write2IntE2], (instregex "MVE_V(MAX|MIN)A?(s|u)")>;
356-
def : InstRW<[M55Write2IntE3], (instregex "MVE_V(MAX|MIN)A?V(s|u)8")>;
356+
def : InstRW<[M55Write2IntE3Plus2], (instregex "MVE_V(MAX|MIN)A?V(s|u)8")>;
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def : InstRW<[M55Write2IntE3Plus1], (instregex "MVE_V(MAX|MIN)A?V(s|u)16")>;
358-
def : InstRW<[M55Write2IntE3Plus2], (instregex "MVE_V(MAX|MIN)A?V(s|u)32")>;
358+
def : InstRW<[M55Write2IntE3], (instregex "MVE_V(MAX|MIN)A?V(s|u)32")>;
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def : InstRW<[M55Write2IntE4NoFwd], (instregex "MVE_VMOVN")>;
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def : InstRW<[M55Write2IntE2], (instregex "MVE_VMOVL")>;
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def : InstRW<[M55Write2IntE3], (instregex "MVE_VMULL[BT]p")>;

‎llvm/test/tools/llvm-mca/ARM/m55-mve-int.s

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -631,15 +631,15 @@ vsub.i32 q0, q2, r0
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# CHECK-NEXT: 1 1 2.00 vmaxa.s8 q0, q2
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# CHECK-NEXT: 1 1 2.00 vmaxa.s16 q0, q2
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# CHECK-NEXT: 1 1 2.00 vmaxa.s32 q0, q2
634-
# CHECK-NEXT: 1 2 2.00 vmaxv.s8 r0, q2
635-
# CHECK-NEXT: 1 2 2.00 vmaxv.u8 r0, q2
634+
# CHECK-NEXT: 1 4 2.00 vmaxv.s8 r0, q2
635+
# CHECK-NEXT: 1 4 2.00 vmaxv.u8 r0, q2
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# CHECK-NEXT: 1 3 2.00 vmaxv.s16 r0, q2
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# CHECK-NEXT: 1 3 2.00 vmaxv.u16 r0, q2
638-
# CHECK-NEXT: 1 4 2.00 vmaxv.s32 r0, q2
639-
# CHECK-NEXT: 1 4 2.00 vmaxv.u32 r0, q2
640-
# CHECK-NEXT: 1 2 2.00 vmaxav.s8 r0, q2
638+
# CHECK-NEXT: 1 2 2.00 vmaxv.s32 r0, q2
639+
# CHECK-NEXT: 1 2 2.00 vmaxv.u32 r0, q2
640+
# CHECK-NEXT: 1 4 2.00 vmaxav.s8 r0, q2
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# CHECK-NEXT: 1 3 2.00 vmaxav.s16 r0, q2
642-
# CHECK-NEXT: 1 4 2.00 vmaxav.s32 r0, q2
642+
# CHECK-NEXT: 1 2 2.00 vmaxav.s32 r0, q2
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# CHECK-NEXT: 1 1 2.00 vmin.s8 q0, q2, q1
644644
# CHECK-NEXT: 1 1 2.00 vmin.u8 q0, q2, q1
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# CHECK-NEXT: 1 1 2.00 vmin.s16 q0, q2, q1
@@ -649,15 +649,15 @@ vsub.i32 q0, q2, r0
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# CHECK-NEXT: 1 1 2.00 vmina.s8 q0, q2
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# CHECK-NEXT: 1 1 2.00 vmina.s16 q0, q2
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# CHECK-NEXT: 1 1 2.00 vmina.s32 q0, q2
652-
# CHECK-NEXT: 1 2 2.00 vminv.s8 r0, q2
653-
# CHECK-NEXT: 1 2 2.00 vminv.u8 r0, q2
652+
# CHECK-NEXT: 1 4 2.00 vminv.s8 r0, q2
653+
# CHECK-NEXT: 1 4 2.00 vminv.u8 r0, q2
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# CHECK-NEXT: 1 3 2.00 vminv.s16 r0, q2
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# CHECK-NEXT: 1 3 2.00 vminv.u16 r0, q2
656-
# CHECK-NEXT: 1 4 2.00 vminv.s32 r0, q2
657-
# CHECK-NEXT: 1 4 2.00 vminv.u32 r0, q2
658-
# CHECK-NEXT: 1 2 2.00 vminav.s8 r0, q2
656+
# CHECK-NEXT: 1 2 2.00 vminv.s32 r0, q2
657+
# CHECK-NEXT: 1 2 2.00 vminv.u32 r0, q2
658+
# CHECK-NEXT: 1 4 2.00 vminav.s8 r0, q2
659659
# CHECK-NEXT: 1 3 2.00 vminav.s16 r0, q2
660-
# CHECK-NEXT: 1 4 2.00 vminav.s32 r0, q2
660+
# CHECK-NEXT: 1 2 2.00 vminav.s32 r0, q2
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# CHECK-NEXT: 1 2 2.00 vmla.i8 q0, q2, r0
662662
# CHECK-NEXT: 1 2 2.00 vmla.i16 q0, q2, r0
663663
# CHECK-NEXT: 1 2 2.00 vmla.i32 q0, q2, r0

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