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Add asserts that the subvector size is a power of 2
This is an invariant needed if we want to check that the subvector exactly fills a vector register by checking if it's a multiple of vlen.
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llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

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@@ -2105,6 +2105,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
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bool ExactlyVecRegSized =
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Subtarget->expandVScale(SubVecVT.getSizeInBits())
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.isKnownMultipleOf(Subtarget->expandVScale(VecRegSize));
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assert(isPowerOf2_64(Subtarget->expandVScale(SubVecVT.getSizeInBits())
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.getKnownMinValue()));
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assert(Idx == 0 && (ExactlyVecRegSized || V.isUndef()));
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#endif
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}

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -9858,6 +9858,8 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
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}
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TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock);
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assert(isPowerOf2_64(
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Subtarget.expandVScale(SubVecVT.getSizeInBits()).getKnownMinValue()));
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bool ExactlyVecRegSized =
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Subtarget.expandVScale(SubVecVT.getSizeInBits())
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.isKnownMultipleOf(Subtarget.expandVScale(VecRegSize));

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